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16 - bit, 12 gsps, rf dac and direct digital synthesizer data sheet AD9164 rev. a document feedback infor mation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specificati ons subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9 106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 2016 2017 analog devices, inc. all rights reserved. technical support www.analog.com features dac update rate up to 1 2 gsps (minimum) direct rf synthesis at 6 gsps (minimum) dc to 2.5 ghz in baseband mode dc to 6 ghz in 2 nonreturn - to - zero ( nrz ) mode 1.5 ghz to 7.5 g hz in mix - m ode bypass able i nterpolation 2, 3, 4, 6 , 8 , 12 , 16 , 24 excellent dynamic performance applications broadband communications systems docsis 3.1 cable modem termination system ( cmts ) / video on demand ( vod ) / edge quadrature amplitude modulation ( eqam ) wireless c ommunications i nfrastructure w - c d m a, lt e, lt e - a, p oint to point general description the AD9164 1 is a high performance, 16- bit digital - to - analog converter (dac ) and direct digital synthesizer (dds) that supports update rates to 6 gsps. the d ac core is based on a quad - switch architecture coupled with a 2 i nterpolator filter that enables an effective dac update rate of up to 12 gsps in some modes . the high dynamic range and bandwidth makes th ese dac s ideally suited for the most demanding high speed ra dio frequency ( rf ) dac applications. the dds consists of a bank of 32, 32- bit n umerically controlled oscillator s (nco s) , each with its own phase accumulator. when combined with a 100 mhz serial peripheral interface (spi) and fast hop modes, phase coheren t fast frequency hopping (ffh) is enabled, with several modes to support multiple applications. in baseband mode, w ide analog bandwidth capability combines with high dynamic range to support docsis 3.1 cable infrastruc - tu re compliance from the minimum of one carrier up to the full maximum spectrum of 1 .791 ghz of signal bandwidth . a 2 i nterpolator filter (fir85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. in mix - mode? operation, the AD9164 can reconstruct rf carriers in the second and third nyquist zones up to 7.5 ghz while still maintainin g exceptional dynamic range. the output current can be programmed from 8 ma to 38 .76 ma. the AD9164 data interface consists of up to eight jesd204b serializer/deserializer ( serdes ) lanes that are prog rammable in terms of lane speed and number of lanes to enable application flexibility. a n spi interface configure s the AD9164 and monitor s the stat us of all registers. the AD9164 is offered in an 165 - ball, 8 mm 8 mm, 0.5 mm pitch csp_bga package, and an 169- ball, 11 mm 11 mm, 0.8 mm pitch , csp_bga package , including a leaded ball option . product highlights 1. high dynamic range and signal reconst ruction bandwidth support s rf signal synthesis of up to 7.5 ghz . 2. up to eight lanes jesd204b serdes interface flexible in terms of number of lanes and lane speed . 3. bandwidth and dynamic range to meet docsis 3.1 compliance and multi band wireless communication s standards with margin. functional block dia gram hb 2 hb 3 jesd hb 2, 4, 8 inv sinc data latch sdo sdio sclk cs spi dac core serdin0 serdin7 sysref syncout clock distribution clk AD9164 to jesd to datapath tx_enable output reset irq vref iset vref nco hb 2 nrz rz mix 14414-001 figure 1. 1 protected by u.s. patents 6,842,132 and 7,796,971.
AD9164* product page quick links last content update: 01/10/2017 comparable parts view a parametric search of comparable parts evaluation kits ? ad9161/ad9162/ad9163/AD9164 evaluation board documentation data sheet ? AD9164 16-bit, 12 gsps, rf dac and direct digital synthesizer data sheet tools and simulations ? AD9164bbcaz ibis model ? AD9164bbcz ibis model reference materials press ? d/a converter offers more accuracy in a smaller footprint for diverse applications ranging from radar to smartphone testing design resources ? AD9164 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD9164 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
AD9164 data sheet rev. a | page 2 of 136 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 dac input clock overclocking specifications ........................ 5 power supply dc specifications ................................................ 5 serial port and cmos pin specifications ................................. 7 jesd204b serial interface speed specifications ...................... 8 sysref to dac clock timing specifications ....................... 8 digital input data timing specifications ................................. 9 jesd204b interface elect rical specifications ........................... 9 ac specifications ........................................................................ 10 absolute maximum ratings .......................................................... 11 reflow profile .............................................................................. 11 thermal management ............................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 16 static l inearity ............................................................................ 16 ac performance (nrz mode) ................................................. 17 ac (mix - mode) .......................................................................... 22 docsis performance (nrz mode) ........................................ 25 terminology .................................................................................... 30 theory of operation ...................................................................... 31 serial port operation ..................................................................... 32 data format ................................................................................ 32 serial port pin descriptions ...................................................... 32 serial port options ..................................................................... 32 jesd204b serial data interface .................................................... 34 jesd204b overview .................................................................. 34 physical layer ............................................................................. 35 data link layer .......................................................................... 38 transport layer .......................................................................... 46 jesd204b test modes ............................................................... 48 jesd204b error monitoring ..................................................... 50 hardware considerations ......................................................... 52 main digital datapath ................................................................... 53 data format ................................................................................ 53 interpolation filters ................................................................... 53 digital modulation ..................................................................... 56 inverse sinc ................................................................................. 58 downstream protection ............................................................ 59 datapath prbs ........................................................................... 59 datapath prbs irq ................................................................... 60 interrupt request operation ........................................................ 61 interrupt service routine .......................................................... 61 applications information .............................................................. 62 hardware consideration s ......................................................... 62 analog interface considerations .................................................. 65 analog modes of operation ..................................................... 65 clock input .................................................................................. 66 shuffle mode ............................................................................... 67 dll ............................................................................................... 67 voltage reference ....................................................................... 67 temperature sensor ................................................................... 67 analog outputs .......................................................................... 68 start - up sequence .......................................................................... 71 register summary .......................................................................... 73 register details ............................................................................... 82 outline dimensions ..................................................................... 135 ordering guide ........................................................................ 136
data sheet AD9164 rev. a | page 3 of 136 revision history 1 /201 7 rev. 0 to rev. a deleted dll_vdd_1p2 parameter, table 1 ................................ ..... 4 added temperature sensor parameter, table 1 ................................ 4 change to endnote 1, table 1 ................................ ................................ . 4 change to output to vneg_n1p2 parameter, table 10 .... 11 changes to link delay se tu p example, with known delays section ................................ ................................ ................................ .......... 4 3 changes to link delay setup example, without known delay section ................................ ................................ ................................ .......... 45 changes to table 24 ................................ ................................ ................. 46 added datapath prbs section ...................................................... 59 add ed datapath prbs irq section ............................................. 60 moved figure 135 ................................ ................................ ..................... 6 7 added temperature sensor section ................................ ....................... 68 changes to equivalent dac output and transfer function section ................................ ................................ ................................ .......... 68 changes to output stage configuration section and figure 142 caption ................................ ................................ ................................ .......... 6 9 added register 0x132 row to re gister 0x135 row, table 45 ... 7 4 added register 0x132 row to register 0x135 row, table 46 ... 91 change to register 0x230 ............................................................... 93 7 /2016 revision 0 : initial version
AD9164 data sheet rev. a | page 4 of 136 s pecifications dc specifications vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , dac output full - scale current ( i outfs ) = 40 ma, and t a = ?40c to +85c, unless otherwise noted . table 1 . parameter test conditions/co mments min typ max unit resolution 1 6 bit dac update rate minimum 1.5 gsps maximum vddx 1 = 1.3 v 2% 2 6 6. 4 gsps vddx 1 = 1.3 v 2% 2 , fi r85 3 2 interpolator enabled 12 12.8 gsps adjusted 4 vddx 1 = 1.3 v 2% 2 6 6.4 gsps accuracy integral non l inearity (inl) 2. 7 lsb differential n on l inearity (dnl) 1.7 lsb analog outputs g ain error (with internal reference) ? 1. 7 % full - scale output current minimum r set = 9. 7 6 k ? 7. 37 8 8. 57 ma maximum r set = 9.76 k? 35. 8 38. 76 4 1.3 ma dac clock input (clk + , clk ? ) differe ntial input power r load = 90 ? diff erential on - chip ? 20 0 +10 dbm common - mode voltage ac - coupled 0.6 v input impedance 1 3 gsps input clock 90 ? temperature drift gain 105 ppm/ c reference vo ltage 75 ppm/c temperature sensor accuracy after single point calibration (see the temperature sensor s ection) 5 % reference internal reference voltage 1. 19 v analog supply voltages vdd25_dac 2.375 2.5 2.625 v vdd 12a 2 1.14 1.2 1.326 v vdd12_clk 2 1.14 1.2 1.326 v vneg_n1p2 ? 1. 26 ? 1.2 ? 1.14 v digital supply voltages dvdd includes vdd12_dcd/dll 1.14 1.2 1.326 v iovdd 3 1.71 2.5 3.465 v serdes supply voltages vdd_1p2 1.14 1.2 1.326 v vtt_1p2 can connect to vdd_1p2 1.14 1.2 1.326 v dvdd_1p2 1.14 1.2 1.326 v pll_ldo_ vdd12 1.14 1.2 1.326 v pll_clk_vdd12 can connect to pll_ldo_vdd12 1.14 1.2 1.326 v sync_vdd_ 3p3 3.135 3.3 3.465 v bias_vdd_1p2 can connect to vdd_1p2 1.14 1.2 1.326 v 1 see the clock input section for more details . 2 for the lowest noise performance, use a separate power supply filter network for the vdd12_clk and the vdd12a pins. 3 io vdd can range from 1.8 v to 3.3 v , with 5% tolerance . 4 the adjusted dac update rate is calculated as f dac divided by the minimum required interpolation factor. for the AD9164 , the minimum interpolation factor is 1. therefore, with f dac = 6 gsps, f dac adjusted = 6 gsps. when fir85 is enabled, which puts the device into 2 nrz mode, f dac = 2 (dac clock input frequency), and the minimum interpolation increases to 2 (interpolation value). thus, for the AD9164 , with fi r85 enabled and dac clock = 6 gsps, f dac = 12 gsps, minimum interpolation = 2 , and the adjusted dac update rate = 6 gsps.
data sheet AD9164 rev. a | page 5 of 136 dac input clock overclocking specifi catio ns vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v, i outfs = 40 ma, t a = ?40c to +85c, unless otherwise noted . maximum guara nteed speed using the temperature and voltage conditions as shown in table 2 , where vddx is vdd12_clk, dvdd, vdd_1p2, dvdd_1p2, and pll_ldo_vdd12. any dac clock speed over 5.1 gsps requires a maximum junction temperature that does not exceed 105c t o av oid damage to the device. see table 10 for details on maximum junction temperature permitted for certain clock speeds. table 2 . parameter 1 test conditions/comments min typ max unit maximum dac update rate vddx = 1.2 v 5% t jmax = 25c 6.0 gsps t jmax = 85c 5.6 gsps t jmax = 105c 5.4 gsps vddx = 1.2 v 2% t jmax = 25c 6.1 gsps t jmax = 85c 5.8 gsps t jmax = 105c 5.6 gsps vddx = 1.3 v 2% t jmax = 25c 6.4 gsps t jmax = 85c 6.2 gsps t jma x = 105c 6.0 gsps 1 t jmax is the maximum junction temperature. power supply dc spec ifications i outfs = 40 ma, t a = ? 40 c to +85 c , unless otherwise noted . fir85 is the finite impulse response with 85 db digital attenuation. table 3 . parameter test conditions/comments min typ max unit 8 lanes, 2 interpolation (80%), 3 gsps nco o n, fir85 o n analog supply currents vdd25_dac = 2.5 v 93.8 100 ma vdd12a = 1.2 v 3.7 150 a vdd12_clk = 1.2 v 229 279 ma vneg_n1p2 = ? 1.2 v ? 119 ? 112 ma digital supply currents dvdd = 1.2 v includes vdd12_dcd/dll 621.3 971 ma iovdd 1 = 2.5 v 2.5 2.7 ma serdes supply currents vdd_1p2 = 1.2 v includes vtt_1p2, bias_vdd_1p2 425.5 550 ma dvdd_1p2 = 1.2 v 62 8 6 ma pll_ldo_vdd12 = 1.2 v connected to pll_clk_vdd12 84.4 106 ma sync_vdd_3p3 = 3.3 v 9.3 11 ma 8 lanes, 6 interpolatio n (80%), 3 gsps nco o n, fir85 o n analog supply currents vdd25_dac = 2.5 v 93.8 ma vdd12a = 1.2 v 3.7 a vdd12_clk = 1.2 v 228.7 ma vneg_n1p2 = ? 1.2 v ? 120.7 ma digital supply currents dvdd = 1.2 v includes vdd12_dcd/dll 598.4 ma iovdd 1 = 2.5 v 2.5 ma
AD9164 data sheet rev. a | page 6 of 136 parameter test conditions/comments min typ max unit serdes supply currents vdd_1p2 = 1.2 v includes vtt_1p2, bias_vdd_1p2 443.4 ma dvdd_1p2 = 1.2 v 72.3 ma pll_ldo_vdd12 = 1.2 v connected to pll_clk_vdd12 81.8 ma sync_vdd_3p3 = 3.3 v 9.4 ma nco only mode, 5 gsps analog supply currents vdd25_dac = 2.5 v 93.7 100 ma vdd12a = 1.2 v 10 150 a vdd12_clk = 1.2 v 340.6 432 ma vneg_n1p2 = ?1.2 v ?119 ?112 ma digital supply currents dvdd = 1.2 v includes vdd12_dcd/dll 425.5 753 ma iovdd 1 = 2.5 v 2.5 2.7 ma serdes supply currents vdd_1p2 = 1.2 v includes vtt_1p2, bias_vdd_1p2 1.4 34 ma dvdd_1p2 = 1.2 v 1.0 14.1 ma pll_ldo_vdd12 = 1.2 v connected to pll_clk_vdd12 0.13 1.5 ma sync_vdd_3p3 = 3.3 v 0.32 0.43 ma 8 lanes, 4 interpolation (80%), 5 gsps nco on, fir85 off (unless otherwise noted) analog sup ply currents vdd25_dac = 2.5 v 102 108 ma vdd12a = 1.2 v 80 150 a vdd12_clk = 1.2 v 340.5 432.4 ma at 6 gsps 408 ma vneg_n1p2 = ?1.2 v ?127.4 ?120.2 ma digital supply currents dvdd = 1.2 v (includes vdd12_dcd/dll) nco on, fir85 off 665.4 1033 ma dvdd = 1.2 v nco off, fir85 on 706.5 ma nco on, fir85 on 894.6 ma nco on, fir85 on, at 6 gsps 1090 ma io vdd 1 = 2.5 v 2.5 2.7 ma serdes supply currents vdd_1p2 = 1.2 v includes vtt_1p2, bias_vdd_1p2 411.2 550 ma dvdd_1p2 = 1.2 v 52.1 73 ma pll_ldo_vdd12 = 1.2 v connected to pll_clk_vdd12 85.8 105 ma sync_vdd_3p3 = 3.3 v 9.3 11 ma 8 lanes, 3 interpolation (80%), 4.5 gsps nco on, fir85 on analog supply currents vdd25_dac = 2.5 v 94 ma vdd12a = 1.2 v 85 175 a vdd12_clk = 1.2 v 314.3 ma vneg_n1p2 = ? 1.2 v ?112.1 ma digital supply currents dvdd = 1.2 v includes vdd12_dcd/dll 948.5 ma iovdd 1 = 2.5 v iovdd = 2.5 v 2.5 ma serdes supply currents vdd_1p2 = 1.2 v includes vtt_1p2, bias_v dd_1p2 432.3 ma dvdd_1p2 = 1.2 v 62.3 ma pll_ldo_vdd12 = 1.2 v connected to pll_clk_vdd12 84.7 ma sync_vdd_3p3 = 3.3 v 9.2 ma
data sheet AD9164 rev. a | page 7 of 136 parameter test conditions/comments min typ max unit power dissipation 3 gsps 2 nrz mode, 6, fir85 enabled, nco on using 80%, 3 filter, eight - lane jesd20 4b 2.1 w nrz mode, 24, fir85 disabled, nco on using 80%, 2 filter, one - lane jesd204b 1.3 w 5 gsps nrz mode, 8, fir85 disabled, nco on using 80%, 2 filter, eight - lane jesd204b 2.18 w nrz mode, 16, fir85 disabled, nco on using 80%, 2 fil ter, eight - lane jesd204b 2.09 w 2 nrz mode, 6, fir85 enabled, nco on using 80%, 3 filter, eight - lane jesd204b 2.65 w 1 io vdd can range from 1.8 v to 3.3 v , with 5% tolerance . serial port and cmos pin specifications vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = ?40c to +85c, unless otherwise noted . table 4 . parameter symbol test comments/conditions min typ max unit write operation see figure 90 maximum sclk clock rate f sclk , 1/t sclk 100 mhz sclk clock high t pw h sclk = 20 mhz 3.5 ns sclk clock low t pwl sclk = 2 0 mhz 4 ns sdio to sclk setup time t ds 4 2 ns sclk to sdio hold time t dh 1 0.5 ns cs to sclk setup time t s 9 1 ns sclk to cs hold time t h 9 0.5 ns read operation see figure 89 sclk clock rate f sclk , 1/t sclk 20 mhz sclk clock high t pw h 20 ns sclk clock low t pwl 20 ns sdio to sclk setup time t ds 10 ns sclk to sdio hold time t dh 5 ns cs to sclk setup time t s 10 ns sclk to sdio (or sdo) data valid time t dv 1 7 ns cs to sdio (or sdo) output valid to high - z not shown in figure 89 or figure 90 45 ns inputs (sdio, sclk, cs , reset , tx_enable ) voltage input high v ih 1.8 v iovdd 2.5 v 0.7 iovdd v low v il 1.8 v iovdd 2.5 v 0.3 iovdd v current input high i ih 75 a low i il ?150 a outputs (sdio, sdo ) voltage output high v oh 1.8 v iovdd 3.3 v 0. 8 iovdd v low v ol 1.8 v iovdd 3.3 v 0. 2 iovdd v current output high i oh 4 ma low i ol 4 ma
AD9164 data sheet rev. a | page 8 of 136 jesd204b serial inte rface speed specific ations vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, i ovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = ?40c to +85c, unless otherwise noted . table 5 . parameter test conditions/comments min typ max unit serial interface speed guara nteed operating range half rate 6 12.5 gbps full rate 3 6.25 gbps oversampling 1.5 3.125 gbps 2 oversampling 0.750 1.5625 gbps sysref to dac clock timing specifications vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = ? 40c to +85c, unless otherwise noted . table 6 . parameter 1 test conditions/comments min typ max unit sysref ( AD9164bbcz o nly ) dc - coupled, common - mode voltage = 1.2 v sysref differential s wing = 0.4 v minimum setup time, t syss 163 424 ps minimum hold time, t sysh 160 318 ps sysref differential s wing = 0.8 v minimum setup time, t syss 162 412 ps minimum hold time, t sysh 169 350 ps sysref differential s wing = 1.0 v minimum setup time, t syss 163 376 ps minimum hold time, t sysh 176 354 ps sysref ( AD9164 bbc a z o nly ) sysref differential s wing = 1.0 v minimum setup time, t syss ac - coupled 65 117 ps dc - coupled, common - mode voltage = 0 v 45 77 ps dc - coupled, common - mode voltage = 1.25 v 68 129 ps minimum h old time, t sysh ac - coupled 19 63 ps dc - coupled, common - mode voltage = 0 v 5 37 ps dc - coupled, common - mode voltage = 1.25 v 51 114 ps 1 the sysref pulse must be at least four dac clock edges wide plus the setup and hold times in table 6 . for more information, see the sync processing modes overview section. sysref+ t syss clk+ t sysh min 4 dac clock edges 14414-002 figure 2 . sysref to dac clock timing diagram ( only sysref+ and clk+ shown )
data sheet AD9164 rev. a | page 9 of 136 digital i nput data timing spe cifications vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = ?40c to +85c, unless otherwise noted. t able 7 . parameter test conditions/comments min typ max unit latency 1 interface 1 p clk 2 cycle interpolation see table 33 power - up time from dac output off to enabled 10 n s deterministic latency fixed 12 p clk 2 cycles variable 2 p clk 2 cycles sysref to local multiframe clocks ( lmfc) delay 4 dac clock cycles 1 total l atency (or pipeline delay) throu gh the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay s ee table 33 for examples of the pipeline delay per block. 2 p clk is the internal proce ssing clock f or the AD9164 a nd equals the lane rate 40. j esd204b interface el ectrical specificati ons vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, vdd_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = ?40c to +85c, unless other wise noted . v tt is the termination voltage. table 8 . parameter symbol test conditions/comments min typ max unit jesd204b data inputs input leakage current t a = 25c logic high input level = 1.2 v 0.25 v, v tt = 1. 2 v 10 a logic low input level = 0 v ?4 a unit interval ui 80 1333 ps common - mode voltage v rcm ac - coupled , v tt = vdd_1p2 1 ?0.05 +1.85 v differential voltage r_v diff 110 1050 mv v tt source impedance z tt at dc 30 ? differential impedanc e z rdiff at dc 80 100 120 ? differential return loss rl rdif 8 db common - mode return loss rl rcm 6 db sysref input differential impedance 165 - ball csp_bga 110 ? 169-b all csp_bga 121 ? differential outputs ( syncout ) 2 driving 100 ? differential load output differential voltage v od 350 420 450 mv output offset voltage v os 1.1 5 1.2 1.27 v 1 as measured o n the input side of the ac coupling capacitor. 2 ieee standard 1596.3 lvds compatible.
AD9164 data sheet rev. a | page 10 of 136 ac s pecifications vdd25_dac = 2.5 v, vdd12a = vdd12_clk = 1.2 v, vneg_n1p2 = ? 1.2 v, dvdd = 1.2 v, iovdd = 2.5 v, v d d_1p2 = dvdd_1p2 = pll_ldo_vdd12 = 1.2 v, sync_vdd_3p3 = 3.3 v , i outfs = 40 ma, t a = + 2 5 c. table 9 . parameter test conditions/comments min typ max unit spurious - free dynamic range (sfdr) 1 single tone , f dac = 5000 msps f out = 7 0 mhz ? 82 dbc f out = 50 0 mhz ? 75 dbc f out = 100 0 mhz ? 65 dbc f out = 2000 mhz ? 70 dbc f out = 4000 mhz fir85 e nabled ?60 dbc single tone, f dac = 5000 msps ?6 dbfs, shuffle enabled f out = 70 mhz ?75 dbc f out = 500 mhz ?75 dbc f out = 10 00 mhz ?70 dbc f out = 2000 mhz ?75 dbc f out = 4000 mhz fir85 enabled ?65 dbc docsis f dac = 3076 msps f out = 70 mhz single carrier ? 70 dbc f out = 70 mhz four carrier s ? 70 dbc f out = 70 mhz eight carrier s ? 67 dbc f out = 950 mhz sing le carrier ? 70 dbc f out = 950 mhz four carrier s ? 68 dbc f out = 950 mhz eight carrier s ? 64 dbc wireless infrastructure f dac = 5000 msps f out = 960 mhz two - carrier gsm signal at ?9 dbfs; across 925 mhz to 960 mhz band ?85 dbc f out = 1990 mhz two - carrier gsm signal at ?9 dbfs; across 1930 mhz to 1990 mhz band ?81 dbc adjacent channel power f dac = 5000 msps f out = 877 mhz one carrier, first adjacent channel ?79 dbc f out = 877 mhz two carriers, first adjacent channel ?76 dbc f out = 1887 mhz one carrier, first adjacent channel ?74 dbc f out = 1980 mhz four carriers, first adjacent channel ?70 dbc intermodulation distortion f dac = 5000 msps, two - tone test f out = 900 mhz 0 dbfs ?80 dbc f out = 900 mhz ?6 dbfs, shuffle enabl ed ?80 dbc f out = 1800 mhz 0 dbfs ?68 dbc f out = 1800 mhz ?6 dbfs, shuffle enabled ?78 dbc noise spectral density (nsd) single tone, f dac = 5000 msps f out = 550 mhz ?168 dbm/hz f out = 960 mhz ?167 dbm/hz f out = 1990 mhz ?164 dbm/hz single sideband (ssb) phase noise at offset f out = 3800 mhz, f dac = 4000 msps 1 khz ?119 dbc/hz 10 khz ?125 dbc/hz 100 khz ?135 dbc/hz 1 mhz ?144 dbc/hz 10 mhz ?156 dbc/hz 1 see the clock input section for more details on opt imizing sfdr and reducing the image of the fundamental with clock input tuning.
data sheet AD9164 rev. a | page 11 of 136 absolute maximum ratings table 10. parameter rating iset, vref to vbg_neg ?0.3 v to vdd25_dac + 0.3 v serdinx, vtt_1p2, syncout ?0.3 v to sync_vdd_3p3 + 0.3 v output to vneg_n1p2 ?0.3 v to vdd25_dac + 0.2 v sysref gnd ? 0.5 v to +2.5 v clk to ground ?0.3 v to vdd12_clk + 0.3 v reset , irq , cs , sclk, sdio, sdo to ground ?0.3 v to iovdd + 0.3 v junction temperature 1 f dac = 6 gsps 105c f dac 5.1 gsps 110c ambient operating temperature range (t a ) ?40c to +85c storage temperature range ?65c to +150c 1 some operating modes of the device may cause the device to approach or exceed the maximum juncti on temperature during operation at supported ambient temperatures. remo val of heat from the device may require additional measures such as active air flow, heat sinks, or other measures. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. reflow profile the AD9164 reflow profile is in accordance with the jedec jesd204b criteria for pb-free devices. the maximum reflow temperature is 260c. thermal management the AD9164 is a high power device that can dissipate nearly 3 w depending on the user application and configuration. because of the power dissipation, the AD9164 uses an exposed die package to give the customer the most effective method of controlling the die temperature. the exposed die allows cooling of the die directly. figure 3 shows the profile view of the device mounted to a user printed circuit board (pcb) and a heat sink (typically the aluminum case) to keep the junction (exposed die) below the maximum junction temperature in table 10. customer case (heat sink) customer thermal filler silicon (die) ic profile package substrate customer pcb 14414-700 figure 3. typical thermal management solution thermal resistance typical ja and jc values are specified for a 4-layer jedec 2s2p high effective thermal conductivity test board for balled surface-mount packages. ja is obtained in still air conditions (jesd51-2). airflow increases heat dissipation, effectively reducing ja . jc is obtained with the test case temperature monitored at the bottom of the package. jt is thermal characteristic parameters obtained with ja in still air test conditions but are not applicable to the csp_bga package. estimate the junction temperature (t j ) using the following equations: t j = t t + ( jt p diss ) where: t t is the temperature measured at the top of the package. p diss is the total device power dissipation. table 11. thermal resistance package type ja jc unit 165-ball csp_bga 15.4 0.04 c/w 169-ball csp_bga 14.6 0.02 c/w esd caution
AD9164 data sheet rev. a | page 12 of 136 pin configuration s and function descrip tions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vneg_n1p2 vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vdd25_dac output ? output+ vdd25_dac vdd25_dac vneg_n1p2 vneg_n1p2 vss vss iset a vss vss vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vdd25_dac vdd25_dac vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vdd12a vdd12a vref b clk+ vss vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vbg_neg vneg_n1p2 vdd25_dac c clk? vss vss vss vss vss d vss vss vss vss vss vdd12_clk e vdd12_clk vdd12_clk vdd12_clk vss vss vss vss vss vdd12_clk vdd12_clk vdd12_clk f irq vss vss vdd12_dcd/ dll vdd12_dcd/ dll vss vdd12_ dcd/dll vdd12_ dcd/dll vss vss cs g vss tx_enable vss vss vss vss vss vss vss sdo vss h serdin7+ vdd_1p2 reset vss vss vss vss vss sclk vdd_1p2 serdin0+ j serdin7? vdd_1p2 iovdd dvdd dvdd dvdd dvdd dvdd sdio vdd_1p2 serdin0? k vss vss dvdd_1p2 dvdd_1p2 vss vss l serdin6+ vdd_1p2 vtt_1p2 vtt_1p2 vdd_1p2 serdin1+ m serdin6? vdd_1p2 sysref+ sysref? vss vss pll_clk_ vdd12 pll_ldo_ vdd12 vss vdd_1p2 serdin1? n vss sync_ vdd_3p3 vdd_1p2 vdd_1p2 dnc vdd_1p2 vdd_1p2 pll_ldo_ bypass vdd_1p2 vdd_1p2 dnc vdd_1p2 vdd_1p2 sync_ vdd_3p3 vss p bias_vdd_ 1p2 vss serdin5+ serdin5? vss serdin4+ serdin4? vss serdin3? serdin3+ vss serdin2? serdin2+ vss bias_ vdd_1p2 r a b c d e f g h j k l m n p r 14414-003 syncout? syncout+ dnc = do not connec t . C 1.2v analog supp l y v 1.2v dac clk supp l y v dac rf signals reference 2.5v analog supp l y v serdes input sysref/syncout 1.2v dac supp l y v serdes 3.3v vco supp l y v cmos i/o iovdd ground serdes 1.2v supp l y v figure 4 . 165- ball csp_bga pin configuration table 12 . 165- ball csp_bg a pin function descriptions pin no. mnemonic description a1, a3, a4, a11, a12, b4, b5, b10, b11, c5, c6, c9, c10, c14 vneg_n1p2 ?1.2 v analog supply voltage. a2, a5, a6, a9, a10, b3, b6, b7, b8, b9, b12, c4, c7, c8, c11, c15 vdd25_dac 2.5 v analog supply voltage. a7 output? dac negative current output. a8 output+ dac positive current output. a13, a14, b1, b2, c2, d2, d3, d13, d 14, d15, e1, e2, e3, e13, e14, f6, f7, f8, f9, f10, g2, g3, g8, g13, g14, h1, h3, h6, h7, h8, h9, h10, h13, h15, j6, j7, j8, j9, j10, l1, l2, l14, l15, n6, n7, n10, p1, p15, r2, r5, r8, r11, r14 vss supply return. connect these pins to ground. a15 iset re ference current. connect this pin to vneg_n1p2 with a 9.6 k? resistor. b13, b14 vdd12a 1.2 v analog supply voltage. b15 vref 1.2 v reference input/output. connect this pin to vss with a 1 f capacitor. c1, d1 clk+, clk? positive and negative dac clock i nputs. c12 vbg_neg ?1.2 v reference. connect this pin to vneg_n1p2 with a 0.1 f capacitor. e15, f1, f2, f3, f13, f14, f15 vdd12_clk 1.2 v clock supply voltage. g1 irq interrupt request output (active low, open drain). g6, g7, g9, g10 vdd12_dcd/dll 1.2 v digital supply voltage.
data sheet AD9164 rev. a | page 13 of 136 pin no. mnemonic description g15 cs serial port chip select bar (active low) input. cmos levels on this pin are determined with respect to iovdd. h14 sdo serial port data output. cmos levels on this pin are determined wi th respect to iovdd. j13 sclk serial port data clock. cmos levels on this pin are determined with respect to iovdd. k13 sdio serial port data input/output. cmos levels on this pin are determined with respect to iovdd. j3 reset reset ba r (active low) input. cmos levels on this pin are determined with respect to iovdd. h2 tx_enable transmit enable input. this pin can be used instead of the dac output bias power - do wn bits in register 0x040, bits [1:0] to enable the dac output. cmos levels are determined with respect to iovdd. p5, p11 dnc do not connect. do not connect to these pins. j2, j14, k2, k14, m2, m14, n2, n14, p3, p4, p6, p7, p9, p10, p12, p13 vdd_1p2 1.2 v serdes digital supply. k3 iovdd supply voltage for cmos input/output and spi. operational for 1.8 v to 3.3 v plus tolerance (see table 1 for details). k6, k7, k8, k9, k10 dvdd 1.2 v digital supply voltage. l3, l13 dvdd_1p2 1.2 v serdes digital supply voltage. m3, m13 vtt_1p2 1.2 v s erdes v tt digital supply voltage. j1, k1 serdin7+, serdin7? serdes lane 7 positive and negative inputs. m1, n1 serdin6+, serdin6? serdes lane 6 positive and negative inputs. r3, r4 serdin5+, serdin5? serdes lane 5 positive and negative inputs. r6, r7 serdin4+, serdin4 - serdes lane 4 positive a nd negative inputs. r9, r10 serdin3?, serdin3+ serdes lane 3 negative and positive inputs. r12, r13 serdin2?, serdin2+ serdes lane 2 negative and positive inputs. m15, n15 serdin1+, serdin1? serdes lane 1 positive and negative inputs. j15, k15 serdin0+ , serdin0? serdes lane 0 positive and negative inputs. n4, n5 sysref+, sysref? system reference positive and negative inputs. these pins are self biased for ac coupling. they can be ac - coupled or dc - coupled. n8 pll_clk_vdd12 1.2 v serdes phase - locked loo p (pll) clock supply voltage. n9 pll_ldo_vdd12 1.2 v serdes pll supply. n11, n12 syncout? , syncout+ negative and positive lvds sync (active low) output signals. p2, p14 sync_vdd_3p3 3.3 v serdes sync supply voltage. p8 pll_ldo_bypass 1.2 v serdes pll supply voltage bypass. r1, r15 bias_vdd_1p2 1.2 v serdes supply voltage.
AD9164 data sheet rev. a | page 14 of 136 1 2 3 4 5 6 7 8 9 10 11 12 13 a vss vneg_n1p2 vdd25_dac vneg_n1p2 vdd25_dac output? output+ vdd25_dac vneg_n1p2 vdd25_dac vss iset vref a b clk+ vss vss vdd25_dac vneg_n1p2 vdd25_dac vdd25_dac vneg_n1p2 vdd25_dac vdd12a vdd12a vdd25_dac vneg_n1p2 b c clk? vss vss vss vdd25_dac vneg_n1p2 vneg_n1p2 vdd25_dac vbg_neg vss vss vss vss c d vss vdd12_clk vdd12_clk vdd12_clk vdd12_clk vss vss vdd12_clk vdd12_clk vdd12_clk vdd12_clk vdd12_clk vdd12_clk d e vdd12_clk vss vss vss dvdd dvdd vss dvdd dvdd vss vss vss vss e f sysref+ sysref? vss vss vss vss vss vss vss vss vss cs vss f g vss vss tx_enable irq dvdd dvdd dvdd dvdd dvdd sdio sdo vss vss g h serdin7+ serdin7? vdd_1p2 reset iovdd dnc dnc dnc dnc dnc dvdd_1p2 vss dvdd_1p2 iovdd sclk vdd_1p2 serdin0? serdin0+ h j vss vss vdd_1p2 vss vss vss syncout? syncout+ vdd_1p2 vss vss j k serdin6+ serdin6? vtt_1p2 sync_ vdd_3p3 vss pll_clk_ vdd12 pll_ldo_ vdd12 sync_ vdd_3p3 vtt_1p2 serdin1? serdin1+ k l vss vss vdd_1p2 vdd_1p2 vdd_1p2 vss vss vdd_1p2 vdd_1p2 vdd_1p2 vss vss l m vss vss serdin5+ vss serdin4+ vss pll_ldo_ bypass vss serdin3+ vss serdin2+ vss vss m n bias_vdd_1p2 vss serdin5? vss serdin4? vss vss vss serdin3? vss serdin2? vss bias_ vdd_1p2 n 1 2 3 4 5 6 7 8 9 10 11 12 13 14414-004 dnc = do not connect. C 1.2v analog supply v 1.2v dac clk supply v dac rf signals 2.5v analog supply v serdes input 1.2v dac supply v serdes 3.3v vco supply v cmos i/o iovdd ground serdes 1.2v supply v sysref/syncout reference figure 5. 169 - ball csp_bga pin configuration table 13. 169 - ball csp_bga pin function descripti ons pin no. mnemonic description a1, a11, b2, b3, c2, c3, c4, c10, c11, c12, c13, d1, d6, d7, e2, e3, e4, e7, e10, e11, e12, e13, f3, f4, f5, f6, f7, f8, f9, f10, f11, f13, g1, g2, g12 , g1 3 , h7, j1, j2, j6, j7, j8, j 12 , j1 3 , k6, l1, l2, l6, l8 , l1 2 , l1 3 , m1, m2, m4, m6, m8, m10, m12, m13, n2, n4, n6, n7, n8, n10, n12 vss supply return. connect these pins to ground. a2 , a4, a9, b5, b8, b13, c6, c7 vneg_n1p2 ? 1.2 v analog supply voltage . a3, a5, a8, a10, b4, b6, b7 , b9, b12, c5, c8 vdd25_dac 2.5 v analog s upply voltage . a 6 output? dac negative current output . a 7 output + dac positive current output . a1 2 iset reference current. connect this pin to vneg_n1p2 with a 9.6 k ? resistor. a13 vref 1.2 v reference input/output. connect this pin to vss with a 1 f capacitor. b1, c1 clk+, clk ? positive and negative dac clock inputs. b10 , b1 1 vdd12a 1.2 v analog supply voltage . c9 vbg_neg ? 1.2 v reference . connect this pin to vneg_n1p2 with a 0.1 f capacitor. d2, d3, d4, d5, d8, d9, d10, d11, d12, d13, e1 vdd12_c lk 1.2 v clock supply voltage . e5, e6, e8, e9, g5, g6, g7, g8, g9 dvdd 1.2 v digital supply voltage .
data sheet AD9164 rev. a | page 15 of 136 pin no. mnemonic description f1, f2 sysref+, sysref ? system reference positive and negative input s . these pins are self biased for ac coupling. they can be ac - coupled or dc - coupled. f12 cs serial port chip select bar (active low) input . cmos levels on this pin are determined with respect to iovdd. g3 tx_enable transmit enable input. this pin can be used instead of t he dac output bias power - down bits in register 0x0 40 , bits [1:0] to enable the dac output. cmos levels are determined with respect to iovdd. g4 irq interrupt request output (active low, open drain) . g10 sdio serial port data input/output. cmos levels on this pin are determined with resp ect to iovdd. g11 sdo serial port data output. cmos levels on this pin are determined with respect to iovdd. h10 sclk serial port data clock. cmos levels on this pin are determined with respect to iovdd. h3, h11, j3, j11, l3, l4, l5, l9, l10, l11 vdd_1p 2 1.2 v serdes digital supply . h4 reset reset bar (active low) input. cmos levels on this pin are determined with respect to iovdd. h5, h9 iovdd supply voltage for cmos input/output and spi. operational for 1.8 v to 3.3 v (s ee table 1 for details ) . h6, h8 dvdd_1p2 1.2 v serdes digital supply voltage . h1, h2 serdi n7+, serdin7 ? serdes lane 7 positive and negative input s . k1, k2 serdin6+, serdin6 ? serdes lane 6 positive and negative inputs. m3, n3 serdin5+, serdin5 ? serdes lane 5 positive and negative inputs. m5, n5 serdin4+, serdin4 ? serdes lane 4 positive and negative inputs. m9, n9 serdin3+, serdin3 ? serdes lane 3 positive and negative inputs. m11, n11 serdin2+, serdin2 ? serdes lane 2 posit ive and negative inputs. k12, k13 serdin1 ? , serdin1+ serdes lane 1 negative and positive input s . h12, h13 serdin0 ? , serdin0+ serdes lane 0 negative and posi tive input s . j4, j5, k5, k9, l7 d n c do no t connect. do n ot c onnect to these pins. j9, j10 syncout? , syncout+ negative and positive lvds sync (active low) output signal s . k3, k11 vtt_1p2 1.2 v serdes v tt digital supply voltage . k4, k10 sync_vdd_3p3 3.3 v serdes sync supply voltage . k7 pll_clk_vdd12 1.2 v serdes p ll clock supply voltage . k8 pll_ldo_vdd12 1.2 v serdes pll supply . m7 pll_ldo_bypass 1.2 v serdes pll supply voltage bypass . n 1, n13 bias_vdd_1p2 1.2 v serdes supply voltage .
AD9164 data sheet rev. a | page 16 of 136 typical performance characteristics static l inearity i outfs = 40 ma, nominal supplies, t a = 25c, unless otherwise noted . 1 5 1 0 i n l ( l s b ) 5 0 ? 5 ?1 0 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 c o d e 4 0 0 0 0 50 0 0 0 6 0 0 0 0 14414-005 figure 6. inl, i outfs = 20 ma 1 5 1 0 i n l ( l s b ) 5 0 ? 5 ? 1 0 0 1 0 0 0 0 2 00 0 0 3 0 0 0 0 c o d e 4 0 0 0 0 5 0 00 0 6 0 0 0 0 14414-006 figure 7. inl, i outfs = 30 ma 1 5 1 0 i n l ( l s b ) 5 0 ? 5 ? 1 0 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 c o d e 4 0 0 0 0 5 0 0 0 0 6 0 00 0 14414-007 figure 8. inl, i outfs = 40 ma 4 2 0 d n l ( l s b ) ? 2 ? 6 ? 4 ? 1 0 ? 8 ? 1 2 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 c o d e 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 14414-008 figure 9. dnl, i outfs = 20 ma 4 ? 2 0 2 ? 4 ? 6 ? 1 0 ? 8 ? 1 2 0 10 0 0 0 2 0 0 0 0 3 0 0 0 0 c o d e 4 00 0 0 5 0 0 0 0 6 0 0 0 0 d n l ( l s b ) 14414-009 figure 10 . dnl, i outfs = 30 ma 4 ? 2 0 2 ? 4 ? 6 ? 1 0 ? 8 ? 1 2 0 10 0 0 0 2 0 00 0 3 0 00 0 c o d e 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 d n l ( l s b ) 14414-010 figure 11 . dnl, i outfs = 40 ma
data sheet AD9164 rev. a | page 17 of 136 ac performance (nrz mode) i outfs = 40 ma, f dac = 5. 0 gsps, nominal supplies, t a = 25c, unless otherwis e noted . 0 ?20 ?40 ?60 ?80 0 1000 2000 3000 4000 5000 frequenc y (mhz) magnitude (dbm) 14414-0 1 1 figure 12 . single - tone spectrum at f out = 70 mhz 0 ?20 ?40 ?60 ?80 0 1000 2000 3000 4000 5000 frequenc y (mhz) magnitude (dbm) 14414-012 figure 13 . single - tone spectrum at f out = 70 mhz (fir85 enabled) ?50 ?60 ?40 f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz ?70 ?80 ?90 ?100 0 1000 500 1500 2000 2500 3000 f out (mhz) sfdr (dbc) 14414-013 figure 14 . sfdr vs. f out over f dac 0 1000 2000 3000 4000 5000 frequenc y (mhz) magnitude (dbm) 0 ?20 ?40 ?60 ?80 14414-014 figu re 15 . single - tone spectrum at f out = 2000 mhz 0 1000 2000 3000 4000 5000 frequenc y (mhz) magnitude (dbm) 0 ?20 ?40 ?60 ?80 14414-015 figure 16 . single - tone spectrum at f out = 2000 mhz (fir85 enabled) 0 1000 500 1500 2000 2500 3000 f out (mhz) imd (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 14414-016 figure 17 . imd vs. f out over f dac
AD9164 data sheet rev. a | page 18 of 136 i outfs = 40 ma, f d ac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise noted . 0 1000 500 1500 2000 2500 f out (mhz) sfdr (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 digi t a l scale = 0db digi t a l scale = ?6db digi t a l scale = ?12db digi t a l scale = ?18db shuffle f alse shuffle true 14414-017 figure 18 . sfdr vs. f out over digital scale 0 1000 500 1500 2000 2500 f out (mhz) in-band second harmonic (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 digi t al scale = 0db digi t al scale = ?6db digi t al scale = ?12db digi t al scale = ?18db shuffle f alse shuffle true 14414-018 figure 19 . sfdr for in - band second harmonic vs. f out over digital scale 0 1000 500 1500 2000 2500 f out (mhz) in-band third harmonic (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 digi t al scale = 0db digi t al scale = ?6db digi t al scale = ?12db digi t al scale = ?18db shuffle f alse shuffle true 14414-019 figure 20 . sfdr for in - band third harmonic vs. f out over digital scale 0 1000 500 1500 2000 2500 f out (mhz) imd (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 digi t al scale = 0db digi t al scale = ?6db digi t al scale = ?12db digi t al scale = ?18db shuffle f alse shuffle true 14414-020 figure 21 . imd vs. f out over digital scale 0 1000 500 1500 2000 2500 f out (mhz) sfdr (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 i outfs = 20m a i outfs = 30m a i outfs = 40m a 14414-021 figure 22 . sfdr vs. f out over dac i outfs 0 1000 500 1500 2000 2500 f out (mhz) imd (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 i outfs = 20m a i outfs = 30m a i outfs = 40m a 14414-022 figure 23 . imd vs. f out over dac i outfs
data sheet AD9164 rev. a | page 19 of 136 i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise noted . 0 1000 500 1500 2000 2500 f out (mhz) sfdr (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 temperature = ?40c temperature = +25c temperature = +85c 14414-023 figure 24 . sfdr vs. f out over temperature f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 400 1800 800 600 1000 1200 1400 1600 2000 f out (mhz) single- t one nsd (dbm/hz) ?160 ?170 ?150 ?155 ?165 ?175 14414-024 figure 25 . single - tone nsd measured at 70 mhz vs. f out over f dac f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 400 1800 800 600 1000 1200 1400 1600 2000 f out (mhz) single- t one nsd (dbm/hz) ?160 ?170 ?150 ?155 ?165 ?175 14414-224 figure 26 . single - tone nsd measured at 10% offset from f out vs. f out over f dac f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 400 1800 800 600 1000 1200 1400 1600 2000 f out (mhz) w -cdm a nsd (dbm/hz) ?160 ?170 ?150 ?155 ?165 ?175 14414-025 figure 27 . w - cdma nsd measured at 70 mhz vs. f out over f dac ?150 ?155 ?160 ?165 ?170 ?175 400 600 800 1000 1200 1400 1600 1800 2000 w -cdm a nsd (dbm/hz) f out (mhz) f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 14414-225 fig ure 28 . w - cdma nsd measured at 10% offset from f out vs. f out over f dac 14414-680 0 1000 500 1500 2000 2500 f out (mhz) imd (dbc) ?50 ?70 ?90 ?40 ?60 ?80 ?100 temper a ture = ?40c temper a ture = +25c temper a ture = +85c figure 29 . imd vs. f out over temperature
AD9164 data sheet rev. a | page 20 of 136 i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise not ed . 400 1000 800 600 1200 1400 1600 1800 2000 f out (mhz) single- t one nsd (dbm/hz) ?155 ?165 ?150 ?160 ?170 ?175 temper a ture = ?40c temper a ture = +25c temper a ture = +90c 14414-027 figure 30 . single - tone nsd measured at 70 mhz vs. f out over temperature 400 1000 800 600 1200 1400 1600 1800 2000 f out (mhz) single- t one nsd (dbm/hz) ?155 ?165 ?150 ?160 ?170 ?175 temper a ture = ?40c temper a ture = +25c temper a ture = +90c 14414-227 figure 31 . single - tone nsd measured at 10% offset from f out vs. f out over temperature 14414-029 figure 32 . single - carrier w - cdma at 877.5 mhz f out (mhz) 400 600 1200 1400 1000 800 2000 1800 1600 ?150 ?155 ?160 ?165 ?170 ?175 w -cdm a nsd (dbm/hz) temper a ture = ?40c temper a ture = +25c temper a ture = +90c 14414-028 figure 33 . w - cdma nsd measured at 70 mhz vs. f out over temperature f out (mhz) 400 600 1200 1400 1000 800 2000 1800 1600 ?150 ?155 ?160 ?165 ?170 ?175 w -cdm a nsd (dbm/hz) temper a ture = ?40c temper a ture = +25c temper a ture = +90c 14414-331 figure 34 . w - cdma nsd measured at 10% offset from f out vs. f out over temperature 14414-032 f igure 35 . two - carrier w - cdma at 875 mhz
data sheet AD9164 rev. a | page 21 of 136 i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise noted . 800 1000 1200 1400 1600 1800 2000 2200 f out (mhz) aclr (dbc) ?70 ?80 ?60 ?65 ?75 ?85 ?90 first aclr second aclr 14414-030 figure 36 . single - carrier, w - cdma adjacent channel leakage ratio (aclr) vs . f out (first aclr, second aclr) 800 1000 1200 1400 1600 1800 2000 2200 f out (mhz) aclr (dbc) ?70 ?80 ?60 ?65 ?75 ?85 ?90 third aclr fourth aclr fifth aclr 14414-031 figure 37 . single - carrier, w - cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr) ssb phase noise (dbc/hz) offset over f out (hz) ?60 ?80 ?100 ?120 ?140 ?160 ?180 10 100 1k 10k 100k 1m 10m 100m 70mhz 900mhz 1800mhz 3900mhz clock source 14414-035 figure 38 . ssb phase noise vs. offset over f out , f dac = 4000 msps (two dif ferent dac clock sources used for best composite curve) 800 1000 1200 1400 1600 1800 2000 2200 f out (mhz) aclr (dbc) ?70 ?80 ?60 ?65 ?75 ?85 ?90 first aclr second aclr 14414-033 figure 39 . two - carrier, w - cdma aclr vs. f out (first aclr, second aclr) 800 1000 1200 1400 1600 1800 2000 2200 f out (mhz) aclr (dbc) ?70 ?80 ?60 ?65 ?75 ?85 ?90 third aclr fourth aclr fifth aclr 14414-034 figure 40 . two - carrier, w - cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr) ssb phase noise (dbc/hz) offset over f out (hz) ?60 ?80 ?100 ?120 ?140 ?160 ?180 10 100 1k 10k 100k 1m 10m 100m 70mhz 900mhz 1800mhz 3900mhz clock source 14414-036 figure 41 . ssb phase noise vs. offset over f out , f dac = 6000 msps
AD9164 data sheet rev. a | page 22 of 136 ac (mix-mode) i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise noted. 02 0 0 0 1000 3000 4000 5000 frequency (mhz) magnitude (dbm) ?20 ?60 0 ?40 ?80 14414-038 figure 42. single-tone spectrum at f out = 2350 mhz 02 0 0 0 1000 3000 4000 5000 frequency (mhz) magnitude (dbm) ?20 ?60 0 ?40 ?80 14414-039 figure 43. single-tone spectrum at f out = 2350 mhz (fir85 enabled) 4000 3000 5000 6000 7000 f out (mhz) single-tone nsd (dbm/hz) ?155 ?165 ? 150 ?160 ?175 ?170 14414-040 figure 44. single-tone nsd vs. f out 0 2000 1000 3000 4000 5000 frequency (mhz) ?20 ?60 ?40 ?80 magnitude (dbm) 0 14414-041 figure 45. single-tone spectrum at f out = 4000 mhz 0 2000 1000 3000 4000 5000 frequency (mhz) ?20 ?60 ?40 ?80 magnitude (dbm) 0 14414-042 figure 46. single-tone spectrum at f out = 4000 mhz (fir85 enabled) ? 150 ?155 ?160 ?165 ?170 ?175 w -cdm a nsd (dbm/hz) 3000 4000 5000 6000 7000 f out (mhz) 14414-599 figure 47. w-cdma nsd vs. f out
data sheet AD9164 rev. a | page 23 of 136 i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless otherwise noted. 4000 2000 3000 5000 6000 8000 7000 f out (mhz) sfdr (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 digi t al scale = 0db digi t al scale = ?6db digi t al scale = ?12db digi t al scale = ?18db shuffle f alse shuffle true 14414-044 figure 48 . sfdr vs. f out over digital scale 4000 2000 3000 5000 6000 8000 7000 f out (mhz) imd (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 digi t al scale = 0db digi t al scale = ?6db digi t al scale = ?12db digi t al scale = ?18db shuffle f alse shuffle true 14414-045 figure 49 . imd vs. f out over digital scale 4000 1000 3000 2000 5000 6000 9000 8000 7000 f out (mhz) sfdr (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 14414-046 figure 50 . sfdr vs. f out over f dac 4000 2000 3000 5000 6000 8000 7000 f out (mhz) sfdr (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 i outfs = 20m a i outfs = 30m a i outfs = 40m a 14414-047 figure 51 . sfdr vs. f out over dac i outfs 4000 2000 3000 5000 6000 8000 7000 f out (mhz) imd (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 i outfs = 20m a i outfs = 30m a i outfs = 40m a 14414-048 figure 52 . imd vs. f out over dac i outfs f dac = 2500mhz f dac = 3000mhz f dac = 5000mhz f dac = 6000mhz 4000 1000 2000 3000 5000 6000 9000 8000 7000 f out (mhz) imd (dbc) ?50 ?60 ?80 ?40 ?70 ?100 ?90 14414-049 figure 53 . imd vs. f out over f dac
AD9164 data sheet rev. a | page 24 of 136 i outfs = 40 ma, f dac = 5.0 gsps, nominal supplies, t a = 25c, unless othe rwise noted. 14414-051 figure 54 . single - carrier w - cdma at 1887.5 mhz 3000 2600 2800 3200 3400 3800 3600 f out (mhz) aclr (dbc) ?65 ?70 ?80 ?60 ?75 ?90 ?85 first aclr second aclr 14414-054 figure 55 . single - carrier, w - cdma aclr vs. f out (first aclr, second aclr) 3000 2600 2800 3200 3400 3800 3600 f out (mhz) aclr (dbc) ?65 ?70 ?80 ?60 ?75 ?90 ?85 third aclr fourth aclr fifth ac l 14414-055 figure 56 . single - carrier, w - cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr) 14414-053 figure 57 . four - carrier w - cdma at 1980 mhz 3200 f out (mhz) 2600 3000 2800 3400 3600 3800 aclr (dbc) ?65 ?70 ?80 ?85 ?60 ?75 ?90 first aclr second aclr 14414-056 figure 58 . four - carrier, w - cdma aclr vs. f out (first aclr, second aclr) 3200 f out (mhz) 2600 3000 2800 3400 3600 3800 aclr (dbc) ?65 ?70 ?80 ?85 ?60 ?75 ?90 third aclr fourth aclr fifth ac l 14414-057 figure 59 . four - carrier, w - cdma aclr vs. f out (third aclr, fourth aclr, fifth aclr)
data sheet AD9164 rev. a | page 25 of 136 docsis performance ( nrz mode) i outfs = 40 ma, f dac = 3.07 6 gsps, nominal supplies, fir85 enabled, t a = 25c, unless otherwise noted. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-058 figure 60 . single carrier at 70 mhz output 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-059 figure 61 . four carriers at 70 mhz output 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-060 figure 62 . eight carriers at 70 mhz output ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 magnitude (dbc) 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) 14414-361 figure 63 . single carrier at 70 mhz output (shuffle on) 0 ?10 ?30 ?40 ?20 ?50 ?60 ?70 ?80 ?90 frequenc y (mhz) magnitude (dbc) 0 500 1000 1500 2000 2500 3000 14414-362 figure 64 . four carriers at 70 mhz output (shuffle on) ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 magnitude (dbc) 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) 14414-363 figure 65 . eight carriers at 70 mhz output (shuffle on)
AD9164 data sheet rev. a | page 26 of 136 i outfs = 40 ma, f dac = 3.076 gsps, nominal supplies, fir85 enabled , t a = 25c, unless otherwise noted. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-061 figure 66 . single carrier at 950 mhz output 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-062 figure 67 . four carriers at 950 mhz output 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-063 figure 68 . eight carriers at 950 mhz output ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 magnitude (dbc) 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) 14414-364 figure 69 . single carrier at 950 mhz output (shuffle on) ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 magnitude (dbc) 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) 14414-365 figure 70 . four carriers at 950 mhz output (shuffle on) ?10 0 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 magnitude (dbc) 0 500 1000 1500 2000 2500 3000 frequenc y (mhz) 14414-366 figure 71 . eight carriers at 950 mhz output (shuffle on)
data sheet AD9164 rev. a | page 27 of 136 i outfs = 40 ma, f dac = 3.076 gsps, nominal supplies, fir85 enabled, t a = 25c, unless otherwise noted. ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band second harmonic (dbc) 14414-064 figure 72 . in - band second harmonic vs. f out performance for one docsis carrier ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band second harmonic (dbc) 14414-065 figure 73 . in - band second harmonic vs. f out performance for four docsis carriers ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band second harmonic (dbc) 14414-066 figure 74 . in - band second harmonic vs. f out performance for eight docsis carriers ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band third harmonic (dbc) 14414-067 figure 75 . in - band third harmonic vs. f out performance for one docsis carrier ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band third harmonic (dbc) 14414-068 figure 76 . in - band third harmonic vs. f out performance for four docsis carriers ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) in-band third harmonic (dbc) 14414-069 figure 77 . in - band third harmonic vs. f out performance for eight docsis carri ers
AD9164 data sheet rev. a | page 28 of 136 i outfs = 40 ma, f dac = 3.076 gsps, nominal supplies, fir85 enabled, t a = 25c, unless otherwise noted. ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) acpr (dbc) y -axis: first acpr y -axis: second acpr y -axis: third acpr y -axis: fourth acpr y -axis: fifth acpr 14414-070 figure 78 . single - carrier adjacent channel power ratio (acpr) vs. f out ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) acpr (dbc) y -axis: first acpr y -axis: second acpr y -axis: third acpr y -axis: fourth acpr y -axis: fifth acpr 14414-071 figure 79 . fou r - carrier acpr vs. f out ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) acpr (dbc) y -axis: first acpr y -axis: second acpr y -axis: third acpr y -axis: fourth acpr y -axis: fifth acpr 14414-072 figure 80 . eight - carrier acpr vs. f out ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) acpr (dbc) y -axis: first acpr y -axis: second acpr y -axis: third acpr y -axis: fourth acpr y -axis: fifth acpr 14414-073 figure 81 . 16 - carrier acpr vs. f out ?40 ?50 ?60 ?70 ?80 ?90 0 400 200 600 800 1000 1200 1400 f out (mhz) acpr (dbc) y -axis: first acpr y -axis: second acpr y -axis: third acpr y -axis: fourth acpr y -axis: fifth acpr 14414-074 figure 82 . 32 - carrier acpr vs. f out 0 ?50 ?40 ?30 ?20 ?10 ?60 ?70 ?80 ?90 0 1000 500 1500 2000 2500 3000 frequenc y (mhz) magnitude (dbc) 14414-075 figure 83 . 194 - carrier, sinc enabled, fir85 enabled
data sheet AD9164 rev. a | page 29 of 136 i outfs = 40 ma, f dac = 3.076 gsps, nominal supplies, fir85 enabled, t a = 25c, unless otherwise noted. ?25 ?35 ?45 ?55 ?65 ?75 ?85 ?95 ?105 ?1 15 ?125 center 77mhz res bw 10khz sp an 60.0mhz swee p 6.041s (1001pts) vbw 1.khz magnitude (dbm) 14414-076 figure 84 . gap channel aclr at 77 mhz ?40 ?50 ?60 ?70 ?80 ?100 ?90 0 400 200 600 800 1000 1200 1400 f gap ( f out = f gap ) (mhz) aclr in ga p channe l (dbc) 14414-077 figure 85 . aclr in gap channel vs. f gap
AD9164 data sheet rev. a | page 30 of 136 terminology integral nonlinearity (inl) inl is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlineari ty (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. offset error offset error is the deviation of the output current from the ideal of 0 ma. for output +, 0 ma output is expected when a ll inputs are set to 0. for output ?, 0 ma output is expected when all inputs are set to 1. gain error gain error is the difference between the actual and ideal output span. the actual span is determined by the difference between the output when the input is at its minimum code and the out put when the input is at its maximum code. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full - scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. settling time settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the sta rt of the output transition. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac. typically, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the dac output. signal -to - noise ratio (snr) snr is the ratio of the rms value of th e measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of the interpolation rate ( f data ), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically a ppear around the output data rate ( f dac ) can be greatly suppressed. adjacent channel leakage ratio (aclr) aclr is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. adjusted dac update rate the adjusted dac update rate i s the dac update rate divided by the smallest interpola ting factor. for clarity on dacs with multiple interpolating factors, the adjusted dac update rate for each interpolating factor may be given. physical lane physical lane x refers to serdinx. logical lane logical lane x refers to physical lanes after opti onally being remapped by the crossbar block (register 0x308 to register 0x30b). link lane link lane x refers to logical lanes considered in the link.
data sheet AD9164 rev. a | page 31 of 136 theory of operation the AD9164 is a 16 - bit single rf dac and digital upconverter with a serdes interface . figure 1 shows a functional block diagram of the AD9164 . eight high speed serial lanes carry da ta at a maximum speed of 12.5 gbps, and either a 5 gsps real input or a 2.5 gsps complex input data rate to the dac. compared to either lvds or cmos interfaces, the serdes interface simplifies pin count, board layout, and input clock requirements to the de vice. the clock for the input data is derived from the dac clock, or device clock (required by the jesd204b specification). this device clock is sourced with a high fidelity direct external dac sampling clock. the performance of the dac can be optimized b y using on - chip adjustments to the clock input accessible through the spi port. the device can be configured to operate in one - lane , two - lane , three - lane , four - lane , six - lane , or eight - lane modes, depending on the required input data rate. the digital dat apath of the AD9164 offers a bypass (1) mode and several interpolation modes (2, 3, 4, 6, 8, 12, 16, and 24) through either an initial half - band (2) or third - band (3) filter with programmab le 80% or 90% bandwidth, and three subsequent half - band filters (all 90%) with a maximum dac samp le rate of 6 gsps. an inverse sinc filter is provided to co mpensate for sinc related roll - off. an additional half - band filter, fir85, takes advantage of the qu ad- switch architecture to interpolate on the falling edge of the clock, and effectively double the dac update rate in 2 nrz mode. a 48 - bit programmable modulus nco is provided to enable digi tal frequency shifts of signals with near infinite precision. the nco can be operated alone in nco only mode or with digital data from the serdes interfac e and digital datapath. the 100 mhz speed of the spi write interface enables rapid updating of the frequency tuning word of the nco. in addition to the main 48 - bi t nco, the AD9164 also offers a ffh nco for selected dds applications . the ffh nco consists of 32, 32- bit ncos, each with its own phase accumulator, a frequency tuning word (ftw) select register to se le ct one of the ncos, and a phase coherent hopping mode; together , these elements enable phase coherent ffh . with the ftw select register and the 100 mhz spi, dwell times as fast as 260 ns can be achieved. the AD9164 dac core provides a fully differential current output with a nominal full - scale current of 38.76 ma. the full - scale output current, i outfs , is user adjustable from 8 ma to 38.76 ma, typically. the differential current outputs are complemen tar y. the dac uses the patented quad - switch architecture, which enables dac decoder options to extend the output frequency range into the second and third nyquist zones with mix - mode , return to zero (rz) mode, and 2 nrz mode (with fir85 enabled). mix - mode can be used to access 1. 5 ghz to around 5 ghz. in the interpolation modes, the output can range from 0 hz to 6 ghz in 2 nrz mode using the nco to shift a signal of up to 1.8 ghz instantaneous bandwidth to the desired f out . the AD9164 is capable of multichip synchronization that can both sy nchronize multiple dacs and establish a constant and determin - istic latency (latency locking) path for the dacs. the latency for each of the dacs remains constant to within several dac clock cycles from link establishment to link establishment. an externa l alignment (sysref) signal makes the AD9164 subclass 1 compliant. several modes of sysref signal handling are available for use in the system. an spi configures the various functional blocks and monitors their statuses. the various functional blocks and the data interface must be set up in a specific sequence for proper oper ation (see the start - up sequence section). simple spi initial ization routines set up the jesd204b link and are included in the evaluation board package. th is data sheet describe s the various blocks of the AD9164 in greater detail. descriptions of the jesd 204b interface, control parameters, and various registers to set up and mo nitor the device are provided. the recommended start - up routine reliably sets up the data link.
AD9164 data sheet rev. a | page 32 of 136 serial port operatio n the serial port is a flexible, synchronous serial communications port that allows easy interfacing with many industry - standard micro controllers and microprocessors. the serial input/output (i/o) is compatible with most synchronous transfer formats, inclu ding both the motorola spi and intel? ssr protocols. the interface allows read/write access to all registers that configure the AD9164 . msb first or lsb first transfer formats are supported. the seria l port interface can be configured as a 4 - wire interface or a 3 - wire interface in which the input and output share a single - pin i/o (sdio) . sclk sdio sdo cs spi port h10 g10 g11 f12 14414-078 figure 86 . serial port interface pins ( 169 - ball csp_bga) there are two phases to a comm unication cycle with the AD9164 . phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 sclk rising edges. the instruction word provides the serial port controller with information regarding the data transfer cycle, phase 2 of the communication cycle. the phase 1 i nstruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the following data transfer. a logic high on the cs pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. from this state, the next 16 rising sclk edges represent the instruction bits of the current i/o operation. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycle is a transfer of one or more data bytes. eight n sclk cycles are needed to transfer n bytes during the transfer cycle. registers change immediately upon writing to the last bit of each transfer byte, except for the ftw and nco phase offsets, which change only when the frequency tuning word ftw_ load _req bit is set. data format the instruction byte contains the information shown in tabl e 14. table 14 . serial port instruction word i15 (msb) i[14:0] r/ w a[14:0] r/ w , bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction w ord write. logic 1 indicates a read operation, and logic 0 indicates a write operation. a14 to a0, bit i 14 to bit i 0 of the instruction word, determine the register that is accessed during the data transfer portion of the communication cycle. for multib yte transfers, a[14:0] is the starting address. the remaining register addresses are generated by the device based on the address increment bit. if the address increment bit s are set high (register 0x000, bit 5 and bit 2), multi - byt e spi writes start on a[ 14:0] and increment by 1 every eight bits sent/received. if the address increment bit s are set to 0, the address decrements by 1 every eight bits. serial port pin desc riptions serial clock (sclk) the serial clock pin synchronizes data to and from the devic e and runs the internal state machines. the maximum frequency of sclk is 10 0 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) an active low input starts and gates a communication cycle. cs allows more than one device to be used on the same serial communications lines. the sdio pin goes to a high impedance state when this input is high. during the communication cycle, the chip select must st ay low. serial data i/o (sdio) this pin is a bidirectional data line. in 4 - wire mode, this pin acts as the data input and sdo acts as the data output. serial port options the serial port can support both msb first and lsb first data formats. this functiona lity is controlled by the lsb first bit (register 0x000, bit 6 and bit 1). the default is msb first (lsb bit = 0). when the lsb first bit s = 0 (msb first), the instruc tion and data bits must be written from msb to lsb. r/ w is followed by a[14:0] as the instruction word, and d[7:0] is the data - word. when the lsb first bits = 1 (lsb first), the opposite is true. a[0:14] is followed by r/ w , which is subsequently followed by d[0:7]. the serial port supports a 3 - wire or 4 - wir e interface. when the sdo active bit s = 1 (register 0x000, bit 4 and bit 3), a 4 - wire interface with a separate input pin (sdio) and output pin (sdo) is used. when the sdo active bits = 0, the sdo pin is unused and the sdio pin is used for both the input a nd the output.
data sheet AD9164 rev. a | page 33 of 136 multibyte data transfers can be performed as well by holding the cs pin low for multiple data transfer cycles (eight sclks) after the first data transfer word following the instruction cycle. the first eight sclks fol lowing the instruction cycle read from or write to the register provided in the instruction cycle. for each additional eight sclk cycles, the address is either incre - mented or decremented and the read/write occurs on the new register. the direction of the address can be set using addrinc or addrinc_m (register 0x000, bit 5 and bit 2). when addrinc or addrinc_m is 1, the multicycle addresses are incremented. when addrinc or addrinc_m is 0, the addresses are decre - mented. a new write cycle can always be initi ated by bringing cs high and then low again. to prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. this test is completed independently fro m the lsb first bit s and ensures that there are extra clock cycles following the soft reset bits (register 0x000, bit 0 and bit 7) . this test of the first nibble only applies when writing to register 0x000. r/w a14 a13 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio cs 14414-079 figure 87 . serial reg ister interface timing, msb first, register 0x000, bit 5 and bit 2 = 0 a0 a1 a2 a12 a13 a14 d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle sclk sdio cs r/w 14414-080 figure 88 . serial register interface timing, lsb first, register 0x000, bit 5 and bit 2 = 1 sclk sdio cs data bit n ? 1 data bit n t dv 14414-081 figure 89 . timing diagram for serial port register read sclk sdio cs instruction bit 14 instruction bit 0 instruction bit 15 t s t ds t dh t pwh t pwl t h 14414-082 figure 90 . timing diagram for serial port register write
AD9164 data sheet rev. a | page 34 of 136 jesd204b serial data interface jesd204b overview the AD9164 has eight jesd204b data ports that receive data. the eight jesd204b ports can be configured as part of a single jesd204b link that use s a single system reference (sysref) and device clock (clk). the jesd204b serial interface hardware consists of three layers: the physical layer , the data link layer, and the transport layer. these sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. figure 91 shows the communic ation layers implemented in the AD9164 serial data interface to recover the clock and deserialize, descramble, and deframe the data before it is sent to the digital signal processing section of the de vice. the physical layer establish es a reliable channel between the transmitter (tx) and the receiver (rx) , the data link layer is responsible for unpacking the data into octets and descrambling the data . t he transport layer receives the descrambled jesd20 4b frames and converts them to dac samples. a number of jesd204b parameters (l, f, k, m, n, n p , s, hd ) define how the data is packed and tell the device how to turn the serial data into samples. these parameters are defined in detail in the transport layer section. the AD9164 also has a descrambling option (see the descrambler section for more information ) . the various combinations of jesd 204b parameters that are supported depend solely on the number of lanes. thus, a unique set of parameters can be determined by selecting the lane count to be used. in addition, the interpolation rate and number of lanes can be used to define the rest of the configura - tion needed to set up the AD9164 . the interpolation rate and the number of lanes are selected in register 0x110. the AD9164 has a single dac output; however , for the purposes of the complex signal processing on chip, the converter count is defined as m = 2 whenever interpolation is used. for a particular application, the number of converters to use (m) and the dat arate variable are known. the lanerate variable and number of lanes (l) can be traded off as follows: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l where lanerate must be between 750 m bps and 12.5 g bps . a chieving and recoverin g synchronization of the lanes is very important. to simplify the interface to the transmitter , the AD9164 designate a master synchronization signal for each jesd204b link. the syncout pin i s used as the master signal for all lanes. if any lane in a link loses synchronization, a resynchronization request is sent to the transmitter via the synchronization signal of the link. the transmitter stops sending data and instead sends synchro nization characters to all lanes in that link until resynchronization is achieved. deserializer dat a link la yer transport la yer serdin0 sysref serdin7 i d at a[15:0] q d at a[15:0] t o dac ds p block syncout physica l la yer deserializer qbd/ descrambler frame t o samples 14414-083 figure 91 . functional block diagram of serial link receiver table 15 . single - link jesd204b operating modes number of l anes (l) parameter 1 2 3 4 6 8 l (lane count) 1 2 3 4 6 8 m (converter count) 2 2 2 2 2 1 ( real ), 2 ( complex ) f (octets per frame per lane) 4 2 4 1 2 1 s (samples per converter per frame) 1 1 3 1 3 4 ( real ), 2 ( complex )
data sheet AD9164 rev. a | page 35 of 136 table 16 . data structure per lane for jesd204b operating modes 1 jesd 204b param eter s lane no. frame 0 frame 1 frame 2 frame 3 l = 8, m = 1, f = 1, s = 4 lane 0 m0s0[15:8] lane 1 m0s0[7:0] lane 2 m0s1[15:8] lane 3 m0s1[7:0] lane 4 m0s2[15 :8] lane 5 m0s2[7:0] lane 6 m0s3[15:8] lane 7 m0s3[7:0] l = 8 , m = 2 , f = 1 , s = 2 lane 0 m0s0[15:8] lane 1 m0s0[7:0] lane 2 m0s1[15:8] lane 3 m0s1[7:0] lane 4 m1s0[15:8] lane 5 m1s0[7:0] lane 6 m1s1[15:8] lane 7 m1s1[7:0] l = 6 , m = 2 , f = 2 , s = 3 lane 0 m0s0[15:8] m0s0[7:0] lane 1 m0s1[15:8] m0s1[7:0] lane 2 m0s2[15:8] m0s2[7:0] lane 3 m1s0[15:8] m1s0[7:0] lane 4 m1s1[15:8] m1s1[7:0] lane 5 m1s2[15:8] m1s2[7:0] l = 4 , m = 2 , f = 1 , s = 1 lane 0 m0s0[15:8] lane 1 m0s0[7:0] lane 2 m1s0[15:8] lane 3 m1s0[7:0] l = 3 , m = 2 , f = 4 , s = 3 lane 0 m0s0[15:8] m0s0[7:0] m0s1[15:8] m0s1[7:0] lane 1 m0s2[15:8] m0s2[7:0] m1s0[15:8] m1s0[7:0] lane 2 m1s1[15:8] m1s1[7 :0] m1s2[15:8] m1s2[7:0] l = 2 , m = 2 , f = 2 , s = 1 lane 0 m0s0[15:8] m0s0[7:0] lane 1 m1s0[15:8] m1s0[7:0] l = 1 , m = 2 , f = 4 , s = 1 lane 0 m0s0[15:8] m0s0[7:0] m1s0[15:8] m1s0[7:0] 1 mx is the converter number and sy is the s ample number. for example, m0s0 means converter 0, sample 0. blank cells are not applicable. physical layer the physical layer of the jesd204b interface , hereafter referred to as the deserializer, has eight identical channels. each channel consists of the terminators, an equalizer, a clock and data recovery (cdr) circuit, and the 1:40 demux function (see figure 92 ). equalizer cdr 1:40 deserializer from serdes pll spi control termination serdinx 14414-084 figure 92 . deserializer block diagram jesd204b data is input to t he AD9164 via the serdinx 1.2 v differential input pins as per the jesd204b specification. interface p ower - up and input termination before using the jesd204b interface, it must be powered up by s etting register 0x200 , bit 0 = 0. in addition, each physical lane (phy) that is not being used (serdinx) must be powered down. to do so, set the corresponding bit x for physical lane x in register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. the AD9164 autocalibrate s the input termination to 50 ?. before running the termination calibration, register 0x2a 7 a nd register 0x2 ae must be written as described in table 17 to guarantee proper calibration. the termination calibration begins when register 0x2a7 , bit 0 and register 0x2ae , bit 0 transition from low to high. register 0x2a7 controls autocalibration for phy 0, phy 1, phy 6, and phy 7. register 0x2ae controls autocalibration for phy 2, phy 3, phy 4, and phy 5.
AD9164 data sheet rev. a | page 36 of 136 the phy termination autocalibration routine i s as shown in table 17. table 17. phy termination autocalibration routine address value description 0x2a7 0x01 autotune phy 0, phy 1, phy 6, and phy 7 terminations 0x2ae 0x01 autotune phy 2, phy 3, phy 4, and phy 5 terminations the input termination voltage of the dac is sourced externally via the v tt_1p2 pins ( ball m3 and ball m13 on the 8 mm 8 mm package, or ball k3 and ball k11 on the 11 mm 11 mm package ). set v tt , the termination v oltage, by connecting it to vdd_1p2 . it is recommended that the jesd204b inputs be ac - coupled to the jesd20 4b transmit device using 100 nf capacitors. the calibration code of the termination can be read from bits [3:0] in register 0x2ac (phy 0, phy 1, phy 6 , phy 7) and register 0x2b3 (phy 2, phy 3, phy 4, phy 5). if needed, the termination values can be adjusted or set using several registers. the term_blkx_ctrlreg1 registers (register 0x2a8 and register 0x2af ) , can override the auto calibrated value. when se t to 0 xxxx0xxxx, the termination block autocalibrate s, which is the normal , default setting. when set to 0xxxx1xxxx, the autocalibration value is overwritten with the value in bits [3:1] of register 0x2a8 and register 0x2af . individual offsets from the auto calibration value for each lane can be programmed in bits [3:0] of register 0x2bb to register 0x2c2. the value is a signed magni - tude, with bit 3 as the sign bit. the total range of the termina tion resistor value is about 94 ? to 120 ? , with approximately 3 .5% increments across the range ( for example , smaller steps at the bottom of the range than at the top). receiver eye mask the AD9164 co mplies with the jesd204b specification regarding the receiver ey e mask and is capable of capturing data that complies with this mask. figure 93 shows the receiver eye mask normalized to the data rate interval with a 600 mv v tt swing. see the jesd204b specification for more info rmation regarding the eye mask and permitted receiver eye opening. 525 55 0 ?55 ?525 amplitude (mv) 0 0.5 1.00 0.35 0.65 time (ui) lv-oif-11g-sr receiver eye mask 14414-085 figure 93 . receiver eye mask for 600 mv v tt swing clock relationships the following clocks rates are used throughout the rest of the jesd204b section. the relat ionship between any of the clocks can be derived from the following equations: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l byterate = lanerate /10 this relationship comes from 8 - bit/10 - bit encoding, where each byte is repres ented by 10 bits. pclk rate = byterate /4 the processing clock is used for a quad - byte decoder. framerate = byterate / f where f is defined as octe ts per frame per lane. p clk factor = framerate / p clk rate = 4/ f where: m is the jesd204b parameter for converte rs per link. l is the jesd204b parameter for lanes per link. f is the jesd204b parameter for octets per frame per lane. serdes pll functional overview of the serdes pll the independent serdes pll uses integer n techniques to achieve clock synthesis. the e ntire serdes pll is integrated on chip, including the vco and the loop filter. the serdes pll vco operates over the range of 6 ghz to 12 .5 ghz. in the serdes pll, a vco divider block divides the vco clock by 2 to generate a 3 ghz to 6 .25 ghz quadrature cl ock for the deserializer cores. this clock is the input to the clock and data recovery block that is described in the clock and data recovery section. the reference clock to the serdes pll is always running at a fr equency, f ref , that is equal to 1/40 of the lane rate ( p clk r ate ) . this clock is divided by a divfactor value (set by serdes_pll_ div_factor ) to deliver a clock to the phase frequency detector ( pfd ) block that is between 3 5 mhz and 80 mhz. table 18 includes the respective serdes_pll_div_ factor register settings for each of the desired pll_ref_clk_rate options available. table 18 . serdes pll divider settings lane rate (gbps) pll_ref_clk_rate , reg ister 0x 0 84 , bits [5:4 ] serdes_pll_div_ factor register 0x289 , bits [1:0] 0.75 0 to 1.5 625 0b01 = 2 0b10 = 1 1. 5 to 3 .125 0b00 = 1 0b10 = 1 3 to 6.25 0b00 = 1 0b01 = 2 6 to 12.5 0b00 = 1 0b00 = 4
data sheet AD9164 rev. a | page 37 of 136 register 0x280 controls the synthesizer enab le and recalibration. to enable the serdes pll, first set the pll divider register (see table 18 ). t hen enable the serdes pll by writing register 0x280 , bit 0 = 1. if a re calibration is needed, write register 0x280 , bit 2 = 0b1 and then reset the bit to 0b0. the rising edge of the bit causes a recalibration to begin. confirm that the serdes pll is working by reading register 0x281. if register 0x281 , bit 0 = 1, the serdes pll has locked. if register 0x281 , bit 3 = 1, the serdes pll was successfully calibrated. if register 0x281 , bit 4 or bit 5 is high, the pll reaches the lower or upper end of its calibration band and must be recalibrated by writing 0 and then 1 to register 0x280 , bit 2. clock and data recovery the deserializer is equipped with a cdr circuit. instead of recovering the clock from the jesd204b serial lanes , the cdr recovers the clocks from the serdes pll. the 3 ghz to 6 .25 ghz output from the serdes pll, shown in figure 94 , is the input to the cdr. a cdr sampling mode must be selected to generate the lane rate clock inside the device. if the desired lane rate is greater than 6.2 5 ghz, half rate cdr operation must be used. if the desired lane rate is less than 6 .25 ghz, disable half rate operation. if the lane rate is less than 3 ghz, disable full rate and enable 2 oversampling to recover the appropriate lane rate clock. table 19 lists the cdr sampling settings that must be set depend ing on the lanerate value . table 19 . cdr operating modes lanerate (gbps) spi_ enhalfrate register 0x230 , bit 5 spi_division_rate , register 0x230 , bits [ 2: 1] 0.75 0 to 1.5 625 0 ( f ull rate) 10b ( d ivide by 4) 1. 5 to 3 .125 0 ( f ull rate) 0 1 b (divide by 2) 3 to 6.25 0 ( f ull rate) 0 0b ( n o divide) 6 to 12.5 1 ( h alf r ate) 0 0b ( n o divide) the cdr circuit synchronizes the phase used to sample the data on each serial lane independently. this independent phase adjustmen t per seria l interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a pcb. after configuring the cdr circuit, reset it and then release the reset by writing 1 and then 0 to register 0x206 , bit 0. power - down unused phys note that any unused and enabled lanes consume extra power unnecessarily. each lane that is not being used (serdinx) must be powered off by writing a 1 to the corresponding bit of phy_pd (register 0x201). equalization to compensate for signal integrity distortions for each phy channel due to pcb trace length and impedance, the AD9164 employ s an easy to use, low power equalizer on each jesd204b channel. the AD9164 equalizers can compensate for in sertion losses far greater than required by the jesd204b specification. the equalizers have two modes of operation that are determined by the eq_power_mode register setting in register 0x268 , bits [7:6]. in low power mode (register 0x268 , bits [7:6] = 2b01) and operating at the maximum lane rate of 12.5 g bps , the equalizer can compensate for up to 11.5 db of insertion loss. in normal mode (register 0x268 , bits [7:6] = 2b00), the equalizer can compensate fo r up to 17.2 db of insertion loss. this performance is shown in figure 95 as an overlay to the jesd204b specification for insertion loss. figure 95 shows the equalization p erformance at 12.5 gbps, near the maxi mum baud rate for the AD9164 . 2 8 pclk gener a t or 4, 2, or 1 cdr oversam p reg 0x289 pl l ref clock v alid range 35mhz t o 80mhz sample clock i, q t o cdr v alid range 3ghz t o 6.25ghz enable half r a te division r a te reg 0x230 jesd lane clock (same r a te as pclk) interpol a tion jesd lanes reg 0x 1 10 pll_ref_clk_r a te 1, 2, 4 reg 0x084 dac clock (5ghz) 6 t o 127, de f au l t : 10 c p lf cdr n 4 mode half r a te ful l r a te, no div ful l r a te, div 2 ful l r a te, div 4 divide (n) 20 40 80 160 14414-086 figure 94 . serdes pll synthesizer block diagram including vco divider block
AD9164 data sheet rev. a | page 38 of 136 figure 96 and figure 97 are provided as points of reference for hardware designers and show the insertion loss for various lengths of well laid out stripline and microstrip t ransmis sion lines , respectively . see the hardware considerations section for specific layout recommendations for the jesd204b channel. low power mode is recommended if the insertion loss of the jesd204b pcb channels is le ss than that of the most lossy supported channel for low power mode (shown in figure 95 ). if the insertion loss is greater than that, but still less than that of the most lossy supported channel for normal mode (sh own in figure 95 ), use normal mode. at 1 2.5 gbps operation, the equalizer in normal mode consumes about 4 mw more power per lane used than in low power equalizer mode. note that either mode can be used in conjuncti on with transmitter preemphasis to ensure functionality and/or optimize for power. i n se r tio n lo ss (d b ) f r e q u e nc y (g h z) 0 2 4 6 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 6.250 9.375 3.125 ad9 164 a ll o w e d chann e l l o s s ( n o r m a l m o d e ) ad9 164 a ll o w e d chann e l l o s s ( l o w p o w e r m o d e ) j es d 204 b spe c a ll o w e d chann e l l o s s ex a m p l e o f j es d 204 b c o m p l i an t chann e l ex a m p l e o f ad9 164 c o m p a t i b l e chann e l ( l o w p o w e r m o d e ) ex a m p l e o f ad9 164 c o m p a t i b l e chann e l ( n o r m a l m o d e ) 14414-087 figure 95 . insertion loss allowed ?4 0 ?3 5 ?3 0 ?2 5 ?2 0 ?1 5 ?1 0 ? 5 0 0 1 2 3 4 5 6 7 8 9 1 0 a tt e n u a t ion ( d b ) f r e q u e n c y ( g h z) stripline = 6" stripline = 10" stripline = 15" stripline = 20" stripline = 25" stripline = 30" 14414-088 figure 96 . insertion loss of 50 striplines on fr4 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 7 8 9 10 a ttenu a tion (db) frequenc y (ghz) 6" microstri p 10" microstri p 15" microstri p 20" microstri p 25" microstri p 30" microstri p 14414-089 figure 97 . insertion loss of 50 microstrips on fr4 data link layer the data link layer of the AD9164 jesd204b interface accepts the deserialized d ata from the phys and deframes , and descrambles them so that data octets are presented to the transport layer to be put into dac samples. the architecture of the data link layer is shown in figure 98. the data link layer consists of a synchronization fifo for each la ne, a crossbar switch, a deframer, and a descrambler. the AD9164 can operate as a single - link high speed jesd204b serial data interface. all eight lanes of the jesd204b interface handle link layer com munications such as code group synchroniza - tion (cgs) , frame alignment, and frame synchronization. the AD9164 decode 8 - bit/10 - bit control characters, allowing marking of the start and end of the fram e and align ment between serial lanes. each AD9164 serial interface link can issue a synchronization request by setting its syncout signal low. the synchronization protocol follows s ection 4.9 of the jesd204b standard. when a stream of four consecutive /k/ symbols is received, the AD9164 deactivates the synchronization request by setting the syncout signal high at the next internal lmfc rising edge. then, AD9164 wait s for the transmitter to issue an initial lane alignment sequence ( ilas ) . during the ilas, all lanes are aligned using the /a/ to /r/ character transition as described in the jesd204b serial link establishment section. elastic buffers hold early arriving lane data until the alignment character of the latest lane arrives. at this point, the buffers for all lanes are released and all lanes are aligned (see figure 99).
data sheet AD9164 rev. a | page 39 of 136 lane 0 deserialized a nd descrambled dat a lane 0 data clock serdin0 fifo serdin7 fifo cross- bar switch lane 7 deserialized a nd descrambled dat a lane 7 data clock pclk data link layer spi control sysref syncoutx descramble 8-bit/10-bit decode system clock phase detect lane 0 octets lane 7 octets quad-byte deframer qbd 14414-090 figure 98. data link layer block diagram l receive lanes (latest arrival) l aligned receive lanes 0 character elastic buffer delay of latest arrival k = k28.5 code group synchronization comma character a = k28.3 lane alignment symbol f = k28.7 frame alignment symbol r = k28.0 start of multiframe q = k28.4 start of link configuration data c = jesd204x link configuration parameters d = dx.y data symbol 4 character elastic buffer delay of earliest arrival l receive lanes (earliest arrival) kkkkkkkrdd kkkrdd ddarqc c ddarqc c ddardd ddardd kkkkkkkrdd ddarqc c ddardd 14414-091 figure 99. lane alignment during ilas jesd204b serial link establishment a brief summary of the high speed serial link establishment process for subclass 1 is provided. see section 5.3.3 of the jesd204b specifications document for complete details. step 1: code group synchronization each receiver must locate /k/ (k28.5) characters in its input data stream. after four consecutive /k/ characters are detected on all link lanes, the receiver block deasserts the syncout signal to the transmitter block at the receiver lmfc edge. the transmitter captures the change in the syncout signal and at a future transmitter lmfc rising edge starts the ilas. step 2: initial lane alignment sequence the main purposes of this phase are to align all the lanes of the link and to verify the parameters of the link. before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. the ilas consists of four or more multiframes. the last character of each multiframe is a multiframe alignment character, /a/. the first, third, and fourth multiframes are populated with predetermined data values. note that section 8.2 of the jesd204b specifications document describes the data ramp that is expected during ilas. the AD9164 does not require this ramp. the deframer uses the final /a/ of each lane to align the ends of the multiframes within the receiver. the second multiframe contains an /r/ (k.28.0), /q/ (k.28.4), and then data corresponding to the link parameters. additional multiframes can be added to the ilas if needed by the receiver. by default, the AD9164 uses four multiframes in the ilas (this can be changed in register 0x478). if using subclass 1, exactly four multiframes must be used. after the last /a/ character of the last ilas, multiframe data begins streaming. the receiver adjusts the position of the /a/ character such that it aligns with the internal lmfc of the receiver at this point.
AD9164 data sheet rev. a | page 40 of 136 step 3: data streaming in this phase, data is streamed from the transmitter block to the receiver block. optionally, data can be scrambled. scrambling does not start until the very first octet following the ilas. the receiver bl ock processes and monitors the data it receives for errors, including the following : ? bad running disparity (8 - bit/10 - bit error) ? not in table (8 - bit/10 - bit error) ? unexpected control character ? bad ilas ? interlane skew error (through character replacement) if any of these errors exist, they are reported back to the transmitter in one of the following ways (see the jesd204b error monitoring section for details): ? syncout signal assertion: resynchronizat ion ( syncout signal pulled low) is requested at each error for the last two errors. for the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold. ? for the first thr ee errors, each multiframe with an error in it causes a small pulse on syncout . ? errors can optionally trigger an interrupt request ( irq ) event, which can be sent to the transmitter. for more information about the v arious test modes f or v erifying the link integrity, see the jesd204b test modes section. lane first in/first out ( fifo ) the fifos in front of the crossbar swit ch and deframer synchro - nize the samples sent on the high speed serial data in terface with the deframer clock by adjusting the phase of the incoming data. the fifo absorbs timing variations between the data source and the deframer; this allows up to two p clk cycles of drift from the transmitter. the fifo_status_reg_0 register and fi fo_status_reg_1 register (register 0x30c and register 0x30d, respectively) can be monitored to identify whether the fifos are full or empty. lane fifo irq an aggregate lane fifo error bit is also available as an irq event. use register 0x0 20 , bit 2 to ena ble the fifo error bit, and then use register 0x02 4 , bit 2 to read back its status and reset the irq signal. see the interrupt request operation section for more information. crossbar switch register 0x308 to register 0x30b allow arbitrary mapping of physical lanes (serdinx) to logical lanes used by the serdes deframers. table 20 . crossbar registers address bits logical lane 0x308 [2:0] src_lane0 0x308 [5:3] src _lane1 0x309 [2:0] sr c _lane2 0x309 [5:3] src _lane3 0x30a [2:0] src _lane4 0x30a [5:3] src _lane5 0x30b [2:0] src _lane6 0x30b [5:3] src _lane7 write each src_laney with the number (x) of the desired physical lane (serdinx) from which to obtain data. by default, all logical lanes use the corresponding physical lane as their data source. for example, by default , src_lane0 = 0 ; therefore , logical lane 0 obtains data from physical lane 0 (serdin0). t o use serdin4 as the source for logical lane 0 instead , the user must write s rc _lane0 = 4. lane inversion register 0x334 allows inversion of desired logical lanes, which can be used to ease routing of the serdinx signals. for each logical lane x, set bit x of register 0x334 to 1 to invert it. deframer the AD9164 consist s of one quad - byte deframer (qbd). the deframer accepts the 8 - bit/10 - bit encoded data from the deserializer (via the crossbar switch), decodes it, and descrambles it into jesd204b frames before passing it to the transport layer to be converted to dac samples. the deframer processes four symbols (or octets) per processing clock ( p clk ) cycle. the deframer uses the jesd204b parameters that the user has programmed into the register map to identify how the data is pac ked , and unpack s it. the jesd204b parameters are described in detail in the transport layer section; many of the parameters are also needed in the transport layer to convert jesd204b frames into samples. descramble r the AD9164 provide s an optional descrambler block using a sel f synchronous descrambler with the following polynomial: 1 + x 14 + x 15 . enabling data scrambling reduces spectral peaks that are produc ed when the same data octets repeat from frame to frame. it also makes the spectrum data independent so that possible frequency selective effects on the electrical interface do not cause data dependent errors. descrambling of the data is enabled by setting the scr bit (register 0x453 , bit 7) to 1.
data sheet AD9164 rev. a | page 41 of 136 syncing lmfc signals the first step in guaranteeing synchronization across links and devices begins with syncing the lmfc signals. in subclass 0, the lmfc signal is synchronized to an internal processing clock. i n subclass 1, lmfc signals are synchronized to an external sysref signal. sysref signal the sysref signal is a differential source synchronous input that synchronizes the lmfc signals in both the transmitter and receiver in a jesd204b subclass 1 syste m to achieve deterministic latency. the sysref signal is a rising edge sensitive signal that is sampled by the device clock rising edge. it is best practice that the device cloc k and sysref signals be generated by the same source, such as the hmc7044 clock generator, so that the phase alignment between the signals is fixed. when designing for optimum deterministic latency operation, consider the timing distribution skew of the sysref signal in a multipoint link system (multichip). the AD9164 support s a periodic sysref signal. the periodicity can be continuous, strobed, or gapped periodic. the sysref signal can always be dc - coupled (with a common - mode voltage of 0 v to 1. 2 5 v). when dc - coupled, a small amount of common - mode current (<500 a) is drawn from the sysref pins. see figure 100 and figure 101 for t he sysref internal circuit. to avoid this common - mode current draw, use a 50% duty cycle periodic sysref signal with ac coupling capacitors. if ac - coupled, the ac coupling capacitors combine with the resistors shown in figure 100 or figure 101 to make a high - pass filter with an rc time constant of = rc. select c such that > 4/sysref f req uency . in addition, the edge rate must be suffi ciently fast to meet the sysref vs. dac clock keep out window (kow) requirements. it is possible to use ac - coupled mode without meeting the frequency to time cons tant constraint s ( = rc and > 4/sysref frequency ) by using sysref hysteresis (register 0x08 8 and register 0x08 9 ). however, using hystereis increases the dac clock kow ( table 6 does not apply) by an amount depe nding on the sysref frequency, level of hysteresis, capacitor choice, and edge rate. 200? 100? 200? sysref+ sysref? 14414-092 figure 100 . sysref i nput circuit for the 8 mm 8 mm 165 - ball bga 3k? 50? sysref+ sysref? 50? 19k? 19k? 3k? 14414-147 figure 101 . sysref input circuit for the 11 m m 11 mm 169 - ball bga sync processing modes overview the AD9164 support s several lmfc sync processing modes. these modes are one shot , continuous , and monitor modes. all sync processing modes perfor m a phase check to confirm that the lmfc is phase aligned to an alignment edge. in subclass 1, the sysref rising edge acts as the alignment edge; in subclass 0, an internal processing clock acts as the alignment edge. the sysref signal is sampled by a d ivide by 4 version of the dac cl oc k . after sysref is sampled, the phase of the ( dac cl oc k ) 4 used to sample sysref is stored in register 0x037 , bits [7:0] and register 0x038 , bits [3:0] as a thermometer code. this offset can be used by the serdes data tra nsmitter ( for example , fpga) to align multiple dacs by accounting for this clock offset when transmitting data. the sync modes are described below. see the sync procedure section for details on the procedure for sy ncing the lmfc signals. one shot sync mode (syncmode = register 0x03a , bits [1:0] = 0b 1 0 ) in one shot sync mode, a phase check occurs on only the first alignment edge that is received after the sync machine is armed. after the phase is aligned on the first edge, the AD9164 transition s to monitor mode. though an lmfc synchronization occurs only once, the sysref signal can still be continuous. in this case, the phase is monitored and reported, but no cl ock phase adjustment occurs. continuous sync mode (syncmode = register 0x03a , bits [1:0] = 0b01 ) continuous mode must be used in subclass 1 only with a periodic sysref signal. in continuous mode, a phase check/alignment occurs on every alignment edge. c on ti nuous mode differs from one shot mode in two ways. first, no spi cycle is required to arm the device; the alignment edge seen after continuous mode is enabled results in a phase check. second, a phase check occurs on every alignment edge in continuous mo de. monitor sync mode (syncmode = register 0x 0 3a , bits [1: 0 ]) = 0b00) in monitor mode, the user can monitor the phase error in real time. use this sync mode with a periodic sysref signal. the phase is monitored and reported, but no clock phase adjustment occurs.
AD9164 data sheet rev. a | page 42 of 136 when an alignment request (sysref edge) occurs, snapshots of the last phase error are placed into readable registers for reference (register 0x037 and register 0x038 , bits [3:0]), and the irq_sysref_jitter interrupt is set, if appropriate. sync p rocedure the procedure for enabling the sync is as follows: 1. set up the dac ; the serdes pll lock s it, and enabl e s the cdr (see the start - up sequence section) . 2. set reg ister 0x 0 39 ( sysref jitter window) . a m inimum of four dac clock cycles is recommended . see table 22 for settings. 3. optional ly, r ead back the sysref count to check whether the sysref pulses are being received. a. set reg ister 0x036 = 0 . w riting anything to sysr ef_count reset s the count. b. set reg ister 0x034 = 0 . writing anything to sync_lmfc_stat0 saves the data for readback and register s the count. c. read sysref_count from the value from register 0x 0 36. 4. perform a one shot sync. a. set register 0x 0 3a = 0x00 . c lear one shot mode if already enabled. b. set register 0x 0 3a = 0x02 . e nable one shot sync mode. the s tate machine enters monitor mode after a sync occurs . 5. optional ly, r ead back the sync sync_lmfc_statx registers to verify that sync completed correctly. a. set register 0x 0 34 = 0 . register 0x034 must be written to read the value . b. r ead reg ister 0x 0 35 and register 0x 0 34 to find the value of sync_lmfc_statx . i t is recommended to set sync_lmfc_statx to 0 but it can be set to 4 , or a lmfc period in dac clocks ? 4 , due to jitter. 6. optional ly, r ead back the sync sysref_phase x register to identify which phase of the divide by 4 was used to sample sysref . read register 0x038 and regi s ter 0x037 as thermom eter code. the msbs of register 0x 0 37, bits[7:4] nor mally show the thermometer code value. 7. turn the link on ( register 0x300 , bit 0 = 1 ) . 8. read back register 0x302 ( d ynamic l ink latency) . 9. repeat the re establishment of the link several times ( step 1 to step 7 ) and note the dynamic link latency values. based on the val ues, program the lmfc delay ( register 0x304) and the lmfc var iable ( register 0x306), and then restart the link. table 21 . sync processing modes sync processing mode sync _ mode (register 0x03a , bits [ 1 :0]) no synchronization 0b00 on e shot 0b10 continuous 0b01 table 22. sysref jitter window tolerance sysref jitter window tolerance (dac clock cycles) sysref_jitter_window (register 0x03 9 , bits [ 5 :0]) 1 ? 0x00 4 0x0 4 8 0x0 8 12 0x0 c 16 0x 10 + 20 0 x 14 +24 0x18 + 28 0x1c 1 the two least significant digits are ignored because the sysref signal is sampled with a divide by 4 version of the dac clock . as a result, the jitter window is set by this divide by 4 clock rather than the dac clock . it is r ecommended that at least a four - d ac clock sysref jitter window be chosen. deterministic latency jesd204b systems contain various clock domains distributed throughout its system. data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the jesd204b link. these ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with each new link establishment. section 6 of the jesd204b specification addresses the issue of deterministic latency with mechanisms defined as subclass 1 and subclass 2. the AD9164 support jesd204b subclass 0 and subclass 1 operation, but not subclass 2. write the subclass to register 0x458 , bits [ 7 : 5 ] . subclass 0 this mode gives deterministic latency to within 32 dac clock cycles. it does not require any signal on the sysref pins, which can be left disconnected. subclass 0 still requires that all lanes arrive within the same lmfc cycle and the dual dacs must be sy nchronized to each other. subclass 1 this mode gives deterministic latency and allows the link to be synced to within four dac clock periods. it requires an external sysref signal that is accurately phase aligned to the dac clock. deterministic latency re quirements several key factors are required for achieving deterministic latency in a jesd204b subclass 1 system. ? sysref signal distribution skew within the system must be less than the desired uncertainty. ? sysref setup and hold time requirements must b e met for each device in the system. ? the total latency variation across all lanes, links , and devices must be 10 p clk periods , which includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in t he system.
data sheet AD9164 rev. a | page 43 of 136 ilas ilas fixed delay variable delay power cycle variance data lmfc aligned data at rx output data at tx input data dsp channel logic device (jesd204b tx) jesd204b rx dac link delay = delay fixed + delay variable 14414-095 figure 102 . jesd204 b link delay = fixed delay + variable delay link delay the link delay of a jesd204b system is the sum of the fixed and variable delays from the transmitter, channel, and receiver as shown in figure 102. for proper functioning, all lanes on a link must be read during the same lmfc period. section 6.1 of the jesd204b specifica - tion states that the lmfc period must be larger than the maximum link delay. for the AD9164 , this is not necessarily the case; instead , the AD9164 use a local lmfc for each link (lmfc rx ) that can be delayed from the sysref a ligned lmfc. because the lmfc is periodic, this delay can account for any amount of fixed delay. as a result, the lmfc period must only be larger than the variation in the link delays, and the AD9164 can achieve proper performance with a smaller total latency. figure 103 and figure 104 show a case where the link delay is greater than an lmfc period. note that it can be accommodated by delaying lmfc rx . ilas data power cycle variance lmfc aligned data early arriving lmfc reference late arriving lmfc reference 14414-093 figure 103 . link delay > lmfc period example ilas data frame clock power cycle variance lmfc aligned data lmfc rx lmfc_delay lmfc reference for all power cycles 14414-094 figure 104 . lmfc_delay _x to compensate for link delay > lmfc the method to select the lmfcdel (register 0x304) and lmfcva r (register 0x306) variables is described in the link delay setup example, w ith known delays section. setting lmfcdel appropriately ensures that all the correspondin g data sa mples arrive in the same lmfc period. then lmfcvar is written into the receive buffer delay (rbd) to absorb all link delay variation . this write ensures that all data samples have arrived before reading. by setting these to fixed values across runs and devices, deterministic latency is achieve d. the rbd described in the jesd204b specification takes values from one frame clock cycle to k f rame c lock cycles, and the rbd of the AD9164 takes values from 0 p clk cycle to 10 p clk cycles. as a res ult, up to 10 p clk cycles of total delay variation can be absorbed. lmfcvar and lmfcdel are both in p clk cycles. the p clk f actor, or number of f rame c lock c ycles per p clk cycle, is equal to 4/f. for more information on this relationship, see the clock relationships section. two examples follow that show how to determine lmfcvar and lmfcdel. after they are calculated, write lmfcdel into register 0x304 for all devices in the system, and write lmfcvar to register 0x30 6 for all devices in the system. link delay setup example, w ith known delays all the known system delays can be used to calculate lmfcvar and lmfcdel. the example shown in figure 105 is demonstrated in the followin g steps. note that this example is in subclass 1 to achieve deterministic latency, which has a p clk f actor (4/f) of two f rame c lock c ycles per p clk c ycle, and uses k = 32 ( frames/multiframe ) . because pcbfixed << p clk period, pcbfixed is negligible in this example and not included in the calculations. 1. find the receiver delays using table 7 . rxfixed = 12 pclk cycles rxvar = 2 pclk cycles 2. find the transmitter delays. the equivalent table in the example jesd 204b core (implemented on a gth or gtx gigabit transceiver on a virtex - 6 fpga) states that the delay is 56 2 byte clock cycles .
AD9164 data sheet rev. a | page 44 of 136 3. because the p clk rate = byterate/4 as described in the clock relationships section, the transmitter delays in p clk cycles are calculated as follows : txfixed = 54/4 = 13.5 p clk cycles txvar = 4/4 = 1 p clk cycle 4. calculate mindelaylane as follows: mindelaylane = floor( rxfixed + txfixed + pcbfixed ) = floor(1 2 + 13.5 + 0) = floor( 25 .5) mindelaylane = 25 5. calculate ma xdelaylane as follows: maxdelaylane = ceiling( rxfixed + rxvar + txfixed + txvar + pcbfixed )) = ceiling(1 2 + 2 + 13.5 + 1 + 0) = ceiling(28 .5) maxdelaylane = 29 6. calculate lmfcvar as follows: lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) = (29 + 1) ? ( 25 ? 1) = 3 0 ? 24 lmfcvar = 6 p clk cycles 7. calculate lmfcdel as follows: lmfcdel = ( mindelay ? 1) % ( k /pclockfactor) = ((30 ? 1)) % ( 32 /2) = 29 % 16 lmfcdel = 13 p clk cycles 8. write lmfcdel to register 0x304 for all devices in the system. write lmfcvar to registe r 0x306 for all devices in the system. frame clock lmfc pclk data data at tx framer ilas lmfc rx total fixed latency = 30 p clk cycles lmfc delay = 26 frame clock cycles pcb fixed delay data aligned lane data at rx deframer output ilas total variable latency = 4 p clk cycles tx var delay rx var delay 14414-096 figure 105 . lmfc delay calculation example
data sheet AD9164 rev. a | page 45 of 136 link delay setup example, without known delay if the system delays are not known, the AD9164 can read back the link latency between lmfc rx for each link and the sysref aligned lmfc. this information is then used to calculate lmfcvar and lmfcdel. figure 107 shows how dyn_link_lat ency _0 (register 0x302 ) provides a readback showing the delay (in pclk cycle s) between lmfc rx and the transition from ilas to the first data sample. by repeatedly power cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate lmfcvar and lmfcdel. in figure 107 , for link a, link b, and link c, the system containing the AD9164 (including the trans mitter) is power cycled and configured 20 times. the AD9164 is configured as described in the sync procedure section. because the purpose of this exercise is to determine lmfcdel and lmfcvar, the lmfcdel value is programmed to 0 and the dyn_link_ latency_0 value is read from register 0x302. the variation in the link latency over the 20 runs is shown in figure 107, descr ibed as follows: ? link a gives readbacks of 6, 7, 0, and 1. note that the set of recorded delay values rolls over the edge of a multiframe at the boundary of k / p clk factor = 8. add the number of p clk cycles per multiframe = 8 to the readback values of 0 an d 1 because they rolled over the edge of the multiframe. delay values range from 6 to 9. ? link b gives delay values from 5 to 7. ? link c gives delay values from 4 to 7. the example shown in figure 107 is demonstrated in the following steps. note that this example is in subclass 1 to achieve deterministic latency, which has a p clk factor ( framerate p clk rate ) of 4 and uses k = 32 ; therefore p clk cycles per multiframe = 8. 1. calculate the minimum of all d elay measureme nts across all power cycles, links, and devices as follows : mindelay = min(all delay values) = 4 2. calculate the maximum of all d elay measurements across all power cycles, links, and devices as follows : maxdelay = max(all delay values) = 9 3. calculate the tota l d elay variation (with guard band) across all power cycles, links, and devices as follows : lmfcvar = ( maxdelay + 1) ? ( mindelay ? 1) = (9 + 1) ? (4 ? 1) = 10 ? 3 = 7 p clk cycles 4. calculate the minimum delay in p clk cycles (with guard band) across all powe r cycles, links, and devices as follows : lmfcdel = ( mindelay ? 1) % ( k / pclk factor ) = (4 ? 1) % 32/4 = 3 % 8 = 3 p clk cycles 5. write lmfcdel to register 0x304 for all devices in the system . write lmfcvar to register 0x306 for all devices in the system. ilas data sysref aligned data lmfc rx dyn_link_latency 14414-097 figure 106 . dyn_link_latency _x illustration 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 dyn_link_latency_cnt aligned data (link a) deterministically delayed data lmfc rx aligned data (link b) aligned data (link c) frame clock lmfc pclk data ilas data ilas data ilas data ilas lmfc_delay = 6 (frame clock cycles) lmfc_var = 7 (p clk cycles) 14414-098 figure 107 . multilink synchronization settings, derived method example
AD9164 data sheet rev. a | page 46 of 136 transport layer delay buffer 1 delay buffer 0 f2s_0 f2s_1 dac a_i0[15:0] dac a_q0[15:0] pclk_1 lane 0 octets lane 7 octets pclk_0 spi control lane 3 octets lane 4 octets dac b_i0[15:0] dac b_q0[15:0] transport layer (qbd) spi control pclk_0 to pclk_1 fifo 14414-099 figure 108 . transport layer block dia gram the transport layer receives the descrambled jesd204b frames and converts them to dac samples based on the programmed jesd204b parameters shown in table 23 . the device parameters are defined in table 24. table 23 . jesd204b transport layer parameters parameter description f number of octets per frame per lane: 1, 2, or 4 k number of frames per multiframe : k = 32 l number of lanes per converte r device (per link), as follows: 4 or 8 m number of converters pe r device (per link), as follows : 1 or 2 ( 1 is used for real data mode; 2 is used for complex data modes ) s number of samples p er converter, per frame: 1 or 2 table 24 . jesd204b device parameters parameter description cf number of control words per device clock per link. not supported, must be 0. cs number of control bits per conversion sample. not supported, must be 0. hd high density user data format. used when samp les must be split across lanes. set to 1 always, even when f does not equal 1 . otherwise, a link configuration error triggers and th e irq_ilas flag is set. n converter resolution = 16. n ? certain combinations of these parameters are supported by the AD9164 . see table 27 for a list of supported interpolation rates and the number of lanes that is supported for each rate . table 27 lists the jesd 204b parameters for each of the interpolation and number of lanes configuration, and gives an example lane rate fo r a 5 ghz dac c lock . table 26 lists jesd204b parameters that have fixed values. a value of yes in table 25 means the interpolation rate is supported for the number of lanes . a blank cell means it is not supported. table 25 . interpolation rates and number of lanes interpolation 8 6 4 3 2 1 1 yes 1 2 yes yes 1 3 yes yes 4 yes yes yes yes 1 6 yes yes yes yes 8 yes yes yes yes y es 12 yes yes yes yes yes 16 yes yes yes yes yes yes 24 yes yes yes yes yes yes 1 these modes restrict the m ax imum dac c lock rate to 5 ghz . table 26 . jesd 204b parameters with fixed values parameter value k 32 n 16 np 16 cf 0 hd 1 cs 0
data sheet AD9164 rev. a | page 47 of 136 table 27. jesd 204b parameters for interpolation rate and number of lanes interp olation rate no . of lanes m f s pclk period (dac clocks ) lmfc period (dac clocks ) lane rate at 5 ghz dac clock ( ghz ) 1 8 1 1 4 16 128 12.5 2 6 2 2 3 12 192 16.66 1 2 8 2 1 2 16 128 12.5 3 6 2 2 3 18 288 11.11 3 8 2 1 2 24 192 8.33 4 3 2 4 3 12 384 16.66 1 4 4 2 1 1 16 128 12.5 4 6 2 2 3 24 384 8.33 4 8 2 1 2 32 256 6.25 6 3 2 4 3 18 576 11.11 6 4 2 1 1 24 192 8.33 6 6 2 2 3 36 576 5.55 6 8 2 1 2 48 384 4.16 8 2 2 2 1 16 256 12.5 8 3 2 4 3 24 768 8.33 8 4 2 1 1 32 256 6.25 8 6 2 2 3 48 768 4.16 8 8 2 1 2 64 512 3.12 12 2 2 2 1 24 384 8.33 12 3 2 4 3 36 1152 5.55 12 4 2 1 1 48 384 4.16 12 6 2 2 3 72 1152 2.77 12 8 2 1 2 96 768 2.08 16 1 2 4 1 16 512 12.5 16 2 2 2 1 32 512 6.25 16 3 2 4 3 48 1536 4.16 16 4 2 1 1 64 512 3.12 16 6 2 2 3 96 1536 2.08 16 8 2 1 2 128 1024 1.56 24 1 2 4 1 24 768 8.33 24 2 2 2 1 48 768 4.16 24 3 2 4 3 72 2304 2.77 24 4 2 1 1 96 768 2.08 24 6 2 2 3 144 2304 1.38 24 8 2 1 2 192 1536 1.04 1 maximum lane rate is 12.5 ghz. these modes must be run with the dac rate below 3.75 ghz.
AD9164 data sheet rev. a | page 48 of 136 configuration parameters the AD9164 modes ref er to the link configuration parameters for l , k , m , n , np , s , and f . table 28 provides the description and addresses for these settings. table 28 . configuration parameters jesd204b setting description address l ? 1 number of lanes minus 1. register 0x453 , bits [4:0] f ? 1 number of ((octets per frame) per lane) minus 1. register 0x454 , bits [7:0] k ? 1 n umber of frames per multiframe ? 1. register 0x455 , bits [4:0] m ? 1 number of conv erters minus 1. register 0x456 , bits[ 7:0] n ? 1 converter bit resolution minus 1. register 0x457 , bits[ 4:0] np ? 1 bit packing per sample minus 1. register 0x458 , bits[ 4:0] s ? 1 number of ((samples per converter) per frame) minus 1. register 0x459 , bits[ 4:0] hd high density format. set to 1 if f = 1. leave at 0 if f 1. register 0x45a , bit 7 did device id. match the d evice id sent by the transmitter. register 0x450 , bits[ 7:0] bid bank id. match the b ank id sent by the transmitter. register 0x451 , bits[ 7 :0] lid0 lane id for lane 0. match the lane id sent by the transmitter on logical lane 0. register 0x452 , bits[ 4:0] jesdv jesd204x v ersion. match the version sent by the transmitter (0x0 = jesd204a, 0x1 = jesd204b). register 0x459 , bits[ 7:5] da ta flow through the jesd204b receiver the link configuration parameters determine how the serial bits on the jesd204b receiver interface are deframed and passed on to the dacs as data samples. deskewing and enabling logical lanes after proper configuratio n, the logical lanes are automatically deskewed . all logical lanes are enabled or not based on the lane number setting in register 0x110 , bits [7:4]. the physical lanes are all powered up by default. t o disable power to physical lanes that are not being use d, set bit x in register 0x201 to 1 to dis able physical lane x , and keep it at 0 to enable it . jesd204b test modes phy prbs testing the jesd204b receiver on the AD9164 includes a prbs pattern che cker on the back end of its physical layer. this functionality enables bit error rate (ber) testing of each physical lane of the jesd204b link. the phy prbs pattern checker does not require that the jesd204b link be established. it can synchronize with a p rbs7, prbs15, or prbs31 data pattern. prbs pattern verification can be done on multiple lanes at once. the error counts for failing lanes are reported for one jesd204b lane at a time. the process for performing prbs testing on the AD9164 is as follows: 1. start sending a prbs7, prbs15, or prbs31 pattern from the jesd204b transmitter. 2. select and write the appropriate prbs pattern to register 0x316 , bits [3:2], as shown in table 29. 3. enable the phy test for all lanes being tested by writing to phy_test_en (register 0x315). each bit of register 0x315 enables the prbs test for the corresponding lane. for exampl e, writing a 1 to bit 0 enables the prbs test for physical la ne 0. 4. toggle phy_test_reset (register 0x316 , bit 0) from 0 to 1 then back to 0. 5. set phy_prbs_test_threshold_ x bits ( bits[23:0], register 0x319 to register 0x317) as desired. 6. write a 0 and then a 1 to phy_test_start (register 0x316 , bit 1). the rising edge o f phy_test_start starts the test. a. (optional) in some cases, it may be necessary to repeat step 4 at this point . toggle phy_test_reset (register 0x316 , bit 0) from 0 to 1 , then back to 0. 7. wait 500 ms. 8. stop the test by writing phy_test_start (register 0x316 , bit 1) = 0. 9. read the prbs test results. a. each bit of phy_prbs_pass (register 0x31d) corresponds to one serdes lane ( 0 = fail, 1 = pass ) . b. the number of prbs errors seen on each failing lane can be read by writing the lane number to check (0 to 7) in phy_sr c_err_cnt (register 0x316 , bits [6:4]) and reading the phy_prbs_err_count (register 0x31c to register 0x31a). the maximum error count is 2 24 ? 1 . if all bits of register 0x31c to register 0x31a are high, the maximum error count on the selected lane is exceeded. table 29 . phy prbs pattern selection phy_prbs_pat_sel setting (register 0x316 , bits [3:2]) prbs pattern 0b00 ( default) prbs7 0b01 prbs15 0b10 prbs31
data sheet AD9164 rev. a | page 49 of 136 transport layer testing the jesd204b receiver in the AD9164 supports the short transport layer (stpl) test as described in the jesd204b standard. this test can be used to verify the data mapping between the jesd204b transmitter and receiver. to perform this test, this function must be implemented in the logic device and enabled there. before running the test on the receiver side, the link must be established and running without errors . the stpl test ensures that each sample from each converter is mapped appropriately according to the number of converters (m) and the number of samples per converter (s). as specified in the jesd204b standard, the converter manuf acturer specifies what test samples are transmitted. each sample must have a unique value. for example, if m = 2 and s = 2, four unique samples are transmitted repeatedly until the test is stopped. the expected sample must be programmed into the device and the expected sample is compared to the received sample one sample at a time until all are tested. the process for performing this test on the AD9164 is described as follows: 1. synchronize the jesd204b link. 2. enable the stpl test at the jesd204b tx. 3. depending on jesd 204b case , there may be up to two dacs, an d each frame may contain up to four dac samples. configure the short_tpl_ref_sp_ msb bits ( register 0x 32e) and short_tpl_ref_sp_lsb bits ( register 0x32 d) to match one of the samples for one converter within one frame. 4. set short_tpl_sp_sel ( register 0x32c , bits [7:4]) to select the sample within one frame for the selected converter according to table 30. 5. set short_ tpl_test_en ( register 0x32c , bit 0 ) to 1. 6. set short_tpl_test_reset (register 0x32c , bit 1) to 1, then back to 0. 7. wait for the desired time . the desired time is calculated as 1/(sample rate ber). for example, given a bit error rate of ber = 1 10 ? 10 and a sample rate = 1 gsps, the desired time = 10 sec. t hen , set short_tpl_test_en to 0. 8. read the test result at short_tpl_fail ( register 0x32f , bit 0). 9. choose another sample for the same or another converter to continue with the test, until all sample s for both converters from one frame are verified. (note that the converter count is m = 2 for all interpolator modes on the AD9164 to enable complex signal processing.) consult table 30 for a guide to the test sample alignment. note that the sample order for 1 , eight - lane mode has sample 1 and sample 2 swapped. also, the stpl test for the three - lane and six - lane options is not functional and always fail s. t able 30 . short tpl test samples assignment 1 jesd204x mode required samples from jesd204x tx samples assignment 1 eight - lane (l = 8, m = 1, f = 1, s = 4) send four samples: m0s0, m0s1, m0s2, m0s3, and repeat sp0: m0s0, sp4: m0s0, s p8: m0s0, sp12: m0s0 sp1: m0s2, sp5: m0s2, sp9: m0s2, sp13: m0s2 sp2: m0s1, sp6: m0s1, sp10: m0s1, sp14: m0s1 sp3: m0s3, sp7: m0s3, sp11: m0s3, sp15: m0s3 2 eight - lane (l = 8, m = 2, f = 1, s = 2) send four samples: m0s0, m0s1, m1s0, m1s1, and r epeat sp0: m0s0, sp4: m0s0, sp8: m0s0, sp12: m0s0 3 eight - lane (l = 8, m = 2, f = 1, s = 2) sp1: m1s0, sp5: m1s0, sp9: m1s0, sp13: m1s0 4 eight - lane (l = 8, m = 2, f = 1, s = 2) sp2: m0s1, sp6: m0s1, sp10: m0s1, sp14: m0s1 6 eight - lane (l = 8, m = 2, f = 1, s = 2) sp3: m1s1, sp7: m1s1, sp11: m1s1, sp15: m1s1 8 eight - lane (l = 8, m = 2, f = 1, s = 2) 12 eight - lane e (l = 8, m = 2, f = 1, s = 2) 16 eight - lane (l = 8, m = 2, f = 1, s = 2) 24 eight - lane (l = 8, m = 2, f = 1, s = 2) 2 six - lane (l = 6, m = 2, f = 2, s = 3) send six samples: m0s0, m0s1, m0s2, m1s0, m1s1, m1s2, and repeat test hardware is not functional; stpl always fail s 3 six - lane (l = 6, m = 2, f = 2, s = 3) 4 six - lane (l = 6, m = 2, f = 2, s = 3) 6 six - lane ( l = 6, m = 2, f = 2, s = 3) 8 six - lane (l = 6, m = 2, f = 2, s = 3) 12 six - lane (l = 6, m = 2, f = 2, s = 3) 16 six - lane (l = 6, m = 2, f = 2, s = 3) 24 six - lane (l = 6, m = 2, f = 2, s = 3) 4 six - lane (l = 3, m = 2, f = 4, s = 3) 6 three - lane (l = 3, m = 2, f = 4, s = 3) 8 three - lane (l = 3, m = 2, f = 4, s = 3) 12 three - lane (l = 3, m = 2, f = 4, s = 3) 16 three - lane (l = 3, m = 2, f = 4, s = 3) 24 three - lane (l = 3, m = 2, f = 4, s = 3)
AD9164 data sheet rev. a | page 50 of 136 jesd204x mode required samples from jesd204x tx samples assignment 4 four - lane (l = 4, m = 2, f = 1, s = 1) send two samples: m0s0, m1s0, repeat sp0: m0s0, sp4: m0s0, sp8: m0s0, sp12: m0s0 6 four - lane (l = 4, m = 2, f = 1, s = 1) sp1: m1s0, sp5: m1s0, sp9: m1s0, sp13: m1s0 8 four - lane (l = 4, m = 2, f = 1, s = 1) sp2: m0s0, sp6: m0s0, sp10 : m0s0, sp14: m0s0 12 four - lane (l = 4, m = 2, f = 1, s = 1) sp3: m1s0, sp7: m1s0, sp11: m1s0, sp15: m1s0 16 four - lane (l = 4, m = 2, f = 1, s = 1) 24 four - lane (l = 4, m = 2, f = 1, s = 1) 8 two - lane (l = 2, m = 2, f = 2, s = 1) 12 two -la ne (l = 2, m = 2, f = 2, s = 1) 16 two - lane (l = 2, m = 2, f = 2, s = 1) 24 two - lane (l = 2, m = 2, f = 2, s = 1) 16 one - lane (l = 1, m = 2, f = 4, s = 1) 24 one - lane (l = 1, m = 2, f = 4, s = 1) 1 mx is the converter number and sy is t he sample number. for example, m0s0 means converter 0, sample 0. spx is the sample pattern word number. for example, sp0 means sample pattern word 0. repeated cgs and ilas test as per section 5.3.3.8.2 of the jesd204b specification, the AD9164 can check that a constant stream of /k28.5/ characters is being received, or that cgs followed by a constant stream of ilas is being received. to run a repeated cgs test, send a constant stream of /k28.5/ char acters to the AD9164 serdes inputs. next, set up the device and enable the links . ensure that the /k28.5/ characters are being received by verifying that syncout is de asserted and t hat cgs has passed for all enabled link lanes by reading register 0x470. to run the cgs followed by a repeated ilas sequence test, follow the procedure to set up the links , but before performing the last write (enabling the links), enable the ilas test mo de by writing a 1 to register 0x477 , bit 7. then, enable the lin ks. when the device recognizes four cgs characters on each lane, it deasserts the syncout . at this point, the transmitter starts sending a repeated ilas sequence. read regi ster 0x473 to verify that initial lane synchronization has passed for all enabled link lanes. jesd204b error monit oring disparity, not in table, and unexpected control ( k) character errors as per section 7.6 of the jesd204b specification, the AD9164 can detect disparity errors, not in table (nit) errors, and unexpected cont rol character errors, and can optionally issue a sync request and reinitialize the link when errors occur. note that the disparity error counter counts all characters with invalid disparity, regardless of whether they are in the 8 - bit/10 - bit decoding tabl e. this is a minor deviation from the jesd204b specification, which only counts disparity errors when they are in the 8 - bit/10 - bit decoding table. several other interpretations of the jesd204b specification are noted in this section . when three nit errors are injected to one lane and qual_rderr ( register 0x476 , bit 4) = 1, the readback values of the bad disparity error ( bde ) c ount register is 1. reporting of disparity errors that occur at the same character position of an nit error is disabled. no such dis abling is per - formed for the disparity errors in the characters after an nit error. therefore , it is expected behavior that an nit error may result in a bde error. a r e sync is triggered when four nit errors are injected with register 0x476 , bit 4 = 1. when this bit is set, the error counter does not distinguish between a concurrent invalid symbol with the wrong running disparity but is in the 8 - bit/10 - bit decoding table , a nd a n nit error. thus, a resync can be triggered when four nit errors are injected bec ause they are not distinguished from disparity errors. checking error counts the error count can be checked for disparity errors, nit errors, and unexpected control character errors. the error counts are on a per lane and per error type basis. each error t ype and lane has a register dedicated to it. to check the error count, the following steps must be performed : 1. choose and enable which errors to monitor by selecting them in register 0x480 , bits [5:3] to register 0x487 , bits [5:3]. unexpected k (uek) characte r, bde, and nit error monitoring can be selected for each lane by writing a 1 to the appropriate bit, as described in the r egister map. these bits are enabled by default. 2. t he corresponding error counter reset bits are in register 0x480 , bits [2:0] to regist er 0x487 , bits [2:0]. write a 0 to the corresponding bit to reset that error counter. 3. registers 0x488 , bits [2:0] to register 0x48f , bits [2:0] have the terminal count hold indicator for each error counter. if this flag is enabled, when the terminal error cou nt of 0xff is reached, the counter cease s counting and hold s that value until reset. otherwise, it wrap s to 0x00 and continue s counting. select the desired behavior and program the corresponding register bits per lane.
data sheet AD9164 rev. a | page 51 of 136 check for error count over threshold to check for the error count over threshold, follow these steps: 1. define the error counter threshold. the error counter t hreshold can be set to a user defined value in register 0x47c, or left to the default value of 0xff. when the error threshold is reached , an irq is generated or syncout is asserted or both, depending on the mask register settings. this one error threshold is used for all three types of errors (uek, nit, and bde). 2. set the sync_assert_mask bits. the syncout assertion behavior is set in register 0x47d , bits [2:0] . by default , when any error counter of any lane is equal to the threshold, it assert s syncout ( register 0x47d , bits [2:0] = 0b111). 3. read the error count reached indicator. each er ror counter has a t erminal c ount r eached indicator, per lane. this indica - tor is set to 1 when the terminal count of an error counter for a particular lane has been reached. these status bits are located in register 0x490 , bits [2:0] to register 0x497 , bits [2:0]. these registers also indicate whether a particular lane is active by setting bit 3 = 0b1. error counter and irq control for error counter and irq control, follow these steps: 1. enable the interrupts. enable the jesd204b i nterrupts . the interrupts for the uek, nit, and bde error counters are in register 0x4b8 , bits [7:5]. there are other interrupts to monitor when bringing up the link , such as lane deskewing, initial lane sync, good check sum, frame sync, code group sync ( register 0x 4b8 , bits [4:0], and c onfiguration mis match ( register 0x4b9 , bit 0) . t hese bits are off by default but can be enabled by writing 0b1 to the corresponding bit. 2. read the jesd204b i nterrupt status. the interrupt status bits are in register 0x4ba , bits [7:0] and register 0x4bb , bit 0, with the status bit position corresponding to the enable bit position. 3. it is recommended to enable all interrupts that are planned to be used prior to bringing up the jesd204b link. when the link is up, the interrupts can be reset and then used to monit or the link status. monitoring errors via syncout when one or more disparity, nit , or unexpected control character error s occur , the error is reported on the syncout pin as per section 7.6 of the jesd204b specification . the jesd204b specification states that the syncout signal is asserted for exactly two frame periods when an error occurs. for the AD9164 , the width of the syncout pulse can be programmed to ?, 1, or 2 p clk cycles. the settings to achieve a syncout pulse of two frame clock cycles are given in table 31. table 31 . setting syncout error pulse duration 1 these register settings assert the syncout signal for two frame cloc k cycle pulse widths. unexpected control character , nit, disparity irqs for uek character, nit , and disparity errors, error count over the threshold events are available as irq events. enable these events by writing to register 0x4 b8 , bits [7:5]. the irq ev ent status can be read at r egister 0x4ba , bits [7:5] after the irqs are enabled. see the error counter and irq control section for information on resetting the irq. see the interrupt request operation section for more information on irqs. errors requiring reinitializing a link reinitialization automatically occurs when four invalid disparity characters are received as per section 7.1 of the jesd 204b s pecification. when a li nk reinitialization occurs, the resync request is five frames and nine octets long. the user can optionally reinitialize the link when the error count for disparity errors, nit errors, or uek character errors reaches a programmable error threshold. the pro cess to enable the reinitialization feature for certain error types is as follows: 1. choose and enable which errors to monitor by selecting them in register 0x480, bits[5:3] to register 0x487 , bits [5:3]. uek, bde, and ni t error monitoring can be selected for each lane by writing a 1 to the appropriate bit, as described in table 46 . these are enabled by default. 2. enable the sync assertion mask for each type of error by writing to syn c_assert_mask (register 0x47d , bits [2 :0 ]) according to table 32 . 3. program the desired error counter threshold into errorthres (register 0x47c). 4. for each error type enabled in the sync_assert_mask register, if the error counter on any lane reaches the programmed threshold, syncout falls, issuing a sync request. note that all error counts are reset when a link reinitialization occurs. the irq does not reset and must be reset manually. table 32 . sync assertion ma sk (sync_assert_mask) addr. bit no. bit name description 0x47d 2 bde set to 1 to assert syncout if the disparity error count reaches the threshold 1 nit set to 1 to assert syncout if the nit error count reaches the threshold 0 uek set to 1 to assert syncout if the uek character error count reaches the threshold f pclk factor (frames/ pclk ) sync _err_dur (register 0x312 , bits [7 :4]) setting 1 1 4 0 (default) 2 2 1 4 1 2
AD9164 data sheet rev. a | page 52 of 136 cgs, frame sync, checksum, and ilas monitoring register 0x470 to register 0x473 can be monitored to verify that each stage of the jesd 204b link establishment has occurred. bit x of code_grp_sync (register 0x470) is high if link lane x received at least four k28.5 characters and passed code group synchronization. bit x of frame_sync (register 0x471) is high if link lane x completed init ial frame synchronization. bit x o f good_checksum (register 0x472) is high if the checksum sent over the l ane matches the sum of the jesd 204b parameter s sent over the lane during ilas for link lane x. the parameters can be added either by summing the indi vidual fields in registers or summing the packed register. if register 0x300 , bit 6 = 0 (default), the calc ulated checksums are the lower eight bits of the sum of the following fields: did, bid, lid, scr, l ? 1, f ? 1, k ? 1, m ? 1, n ? 1, subclassv, np ? 1, jesdv, s ? 1, and hd. if register 0x300 , bit 6 = 1, the calc ulated checksums are the lower eight bits of the sum of register 0x400 to register 0x40c and lid. bit x of init_lane_sync (register 0x473) is high if link lane x passed the initial lane alignment sequence. cgs, frame sync, checksum, and ilas irqs fail signals for cgs, f rame sync, c heck s um, and ilas are available as irq events. enable them by writing to register 0x4b8 , bits [3:0]. the irq event status can be read at register 0x4ba , bits [3:0] after the irqs are enabled. write a 1 to regist er 0x4ba , bit 0 to reset the cgs irq. write a 1 to register 0x4 ba, bit 1 to reset the frame sync irq. write a 1 to register 0x4ba , bit 2 to reset the c heck s um irq. write a 1 to register 0x4ba , bit 3 to reset the ilas irq. see the interrupt request operation section for more information. configuration mismatch irq the AD9164 ha s a configuration mismatch flag that is available as an irq event. use register 0x4b9 , bit 0 to enable the mismatch flag (it is enabled by defa ult), and then use register 0x4 b b , bit 0 to read ba ck its status and reset the irq signal. see the interrupt request operation section for more information. the configuration mismatch event flag is high when the link configuration settings (in register 0x450 to re gister 0x45d) do not match the jesd204b transmitted settings (register 0x400 to register 0x40d). t his function is different from the good checksum flags in register 0x472. the good checksum flags ensure that the transmit - ted checksum matches a calculated checksum based on the transmitted settings. the configuration mismatch event ensures that the transmitted settings match the configured settings. hardware considerati ons see the applications information section for information on hardware considerations.
data sheet AD9164 rev. a | page 53 of 136 main digital datapath h b 2 h b 3 j esd h b 2 , 4 , 8 nc o i n v s i n c h b 2 14414-104 figure 109 . block diagram of the main digital datapath the block diagram in figure 109 shows the functionality of the m ain digital datapath. the digital processing includes an input interpolati on block with choice of bypass 1 , 2 , or 3 interpolation, three additional 2 half - band interpolation filters, a final 2 nrz mode interpolator filter , fir85, that can be bypassed, and a quadrature modulator that consists of a 48- bit nco and an inverse sinc block. all of the interpolation filters accept in - phase ( i ) and quadrature ( q ) data streams as a complex data stream. similarly, the quadrature modulator and inverse sinc functio n also accept input data as a complex data stream. thus, any use of the digital datapath functions requires the input data to be a complex data stream. in bypass mode (1 interpolation), the input data stream is expected to be real data. table 33 . pipeline delay (latency) for various dac blocks mode fir85 on filt er b andwidth inv erse sinc nco pipeline delay 1 (f dac clocks ) nco only no n/a 2 no yes 48 1 (bypass) no n/a 2 no no 113 1 (bypass) no n/a 2 yes no 137 2 no 80% no no 155 2 no 90% no no 176 2 yes 80% no no 202 2 no 80% yes no 185 2 yes 80% yes no 239 2 yes 80% yes yes 279 3 no 80% no no 168 3 no 90% no no 202 4 no 80% no no 308 6 no 80% no no 332 8 no 80% no no 602 12 no 80% no no 674 16 no 80% no no 1188 24 no 80% no no 1272 1 the pipeline delay given is a representative number, and may vary by a cycle or two based on the internal handoff timing conditions at startup. 2 n/a means not applicable. the pipeline delay change s based on the digital dat apath functions that are selected. see table 33 for examples of the pipeline delay per block. these delays are in addition to the jesd204b latency. data format the input data format for all modes on the AD9164 is 16 - bit, two s complement. the digital d atapath and the dac decoder operate in twos complement format . the dac is a current steering dac and cannot represent 0 it must either source or sink current. as a result, when the 0 of twos comple ment is represented in the dac, it is a +1, and all the positive values thereafter are shifted by +1. this mapping error introduces a ? lsb shift in the dac output. the leakage can become apparent when using the nco to sh ift a signal that is above or below 0 hz when synthesized. the nco frequency is seen as a small spur at t h e n c o f t w. to avoid the nco frequency leakage, operate the dac with a slight digital backoff of one or several codes, and then add 1 to all values in the data stream. these actions remove the nco frequency leakage but cause a half lsb dc offset. this small dc offset is benign to the dac and does not affect most applications because the dac output is ac - coupled through dc blocking capacitors. interpolat ion filters the main digital path contains five half - band interpolation filters, plus a final half - band interpolation filter that is used in 2 nrz mode. the filters are cascaded as shown in figure 109. the first pair of filters is a 2 (hb2) or 3 (hb3) filter. each of these filters has two options for bandwidth, 80% or 90%. the 80% filters are lower power than the 90%. the filters default to the lower power 80% bandwidth. to select the filter bandwidth as 90%, pr ogram the filt_bw bit in the datapath_cfg register to 1 (register 0x111 , bit 4 = 0b1). following the first pair of filters is a series of 2 half - band filters, each of which halves the usable bandwidth of the previous one. hb4 has 45% , hb5 has 22.5%, and h b6 has 11.25% of the f data bandwidth. the final half - band filter , fir85, is used in the 2 nrz mode. it is clocked at the 2 f dac rate and has a usable bandwidth of 45% of the f dac rate. the fir85 filter is a complex filter , and therefore the bandwidth i s centered at 0 hz. the fir85 filter is used in conjunction with the complex interpolation modes to push the dac update rate higher and move images further from the desired signal.
AD9164 data sheet rev. a | page 54 of 136 table 34 shows how to select ea ch available interpolation mode, their usable bandwidths, and their maximum data rates. calculate the available signal bandwidth a s the interpolator filter bandwidth, bw, multiplied by f dac /interpolationfactor , as follows: bw signal = bw filt ( f dac / interpo lationfactor ) filter performance the interpolation filters interpolate between existing data in such a way that they minimize changes in the incoming data while suppressing the creation of interpolation images. this datapath is shown for each filter in figure 110. the usable bandwidth (as shown in table 34 ) is defined as the frequency band over which the filters have a pass - band ripple of less than 0.001 db and an image rej ection of greater than 85 db. a conceptual drawing that shows the relative bandwidth of each of the filters is shown in figure 110 . the maximum pass band amplitude of all filters is the same; they are different in the illustration to improve understanding. ?1500 ?500 500 1500 2500 frequenc y (mhz) fi l ter response 1 2 3 4 6 8 12 16 24 fir85 14414-105 figure 110 . all band responses of interpolation filters filter performance beyond specified bandwidth some of the interpolation filters are specified to 0.4 f data (with a pass band). t he filters can be used slightly beyond this ratio at the expense of increased pass - band ripple and decreased interpolation image rejection. 90 20 0 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 30 40 50 60 70 80 40 41 42 43 44 45 minimum interpolation image rejection (db) maximum pass-band ripple (db) bandwidth (% f data ) pass-band ripple image rejection 14414-106 figure 111 . interpolation filter performance beyond specified bandwidth for the 80% filte rs figure 111 shows the performance of the interpolation filters beyond 0.4 f data . the ripple increases much slower than the image rejection decreases. this means that if the application can tolerate degraded ima ge rejection from the interpolation filters, more bandwidth can be used. most of the filters are specified to 0.45 f data (with pass band). figure 112 to figure 119 show t he filter response for each of the interpolator filters on the AD9164 . table 34 . interpolation modes and usable bandwidth interpolation mode interp_mode , reg ister 0x11 0 , bits [ 3 :0] avail able signal bandwidth (bw) 1 max imum f data (mhz) 1 (bypass) 0x00 f dac /2 f dac 2 2 0x01 bw f data /2 f dac /2 2 3 0x02 bw f data /2 f dac /3 4 0x03 bw f data /2 f dac /4 6 0x04 bw f data /2 f dac /6 8 0x05 bw f d ata /2 f dac /8 12 0x06 bw f data /2 f dac /12 16 0x07 bw f data /2 f dac /16 24 0x08 bw f data /2 f dac /24 2 nrz ( register 0x111 , bit 0 = 1) any combination 3 0.45 f dac 4 f dac (real) or f dac /2 (complex) 2 1 the data rate (f data ) for all interp olator modes is a complex data rate, meaning each of i data and q data run at that rate. available signal bandwidth is the da ta rate multiplied by the bandwidth of the initial 2 or 3 interpolator filters, which can be set to bw = 80% or bw = 90%. this ba ndwidth is centered at 0 hz. 2 the maximum speed for 1 and 2 interpolation is limited by the jesd204b interface, and is 5000 mhz (real) in 1 or 2500 mhz (complex) in 2 interpolation mode. 3 the 2 nrz filter, fir85, can be used with any of the interpol ator combinations. 4 the bandwidth of the fir85 filter is centered at 0 hz.
data sheet AD9164 rev. a | page 55 of 136 normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-158 figure 112 . first 2 half - band 80% filter response normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-159 figure 113 . first 2 half - band 90% filter response normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-160 figure 114 . 3 third - band 80% filter response normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-161 figure 115 . 3 third - band 90% filter response normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-162 figure 11 6 . second 2 half - band 45% filter response normalized frequenc y ( rad/sample ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-163 figure 117 . third 2 half - band 22.5% filter response
AD9164 data sheet rev. a | page 56 of 136 normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-164 figure 118 . fourth 2 half - band 11.25% filter response normalized frequenc y (rad/sample) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude (db) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 14414-165 figure 119 . fir85 2 half - band 45% filter response digital modulation the AD9164 ha s digital modulation features to modulate the baseband quadrature signal t o the desired dac output frequency. the AD9164 is equipped with several nco modes . the default nco is a 48 - bit, integer nco. the a/b ratio of the dual modulus nco allows the output frequency to be syn thesized with very fine precision. nco mode is selected as shown in table 35. table 35 . modulation mode selection modulation mode modulation type register 0x111, bit 6 register 0x111, bit 2 none 0b0 0b0 48- bit integer nco 0b1 0b0 48- bit dual modulus nco 0b1 0b1 32- bit ffh nco 0b1 0b1 1 the ffh nc os are enabled by writing a non zero word to their ftw registers wh en the main 48 - bit nco is enabled (see the fast frequency hopping (ffh) section) . the modulus can be enabled or disabled . if the modulus is enabled , the same modulus ratio applies to all the ncos. 48- bit dual modulus nco this modulation mode uses an nco, a phase shifter, and a complex modulator to mo dulate the signal by a programmable carrier signal as shown in figure 120 . this configuration allows output signals to be placed anywhere in the output spectrum with very fine frequency resolution. the nco produces a quadrature carrier to translate the input signal to a new center frequency. a quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the quadrature carrier is set via a f t w. the quadratur e carrier is mixed with the i and q data and then summed into the i and q datapaths, as shown in figure 120 . integer nco mode the main 48 - bit nco can be used as an integer nco by using the following formula to crea te the frequency tuning word (ftw): ? f dac /2 f carrier < + f dac /2 ftw = ( f carrier / f dac ) 2 48 where ftw is a 48 - bit , twos complement number. when in 2 nrz mode (fir85 enabled with register 0x111 , bit 0 = 1), the frequency tuning word is calculated as 0 f carrier < f dac ftw = ( f carrier / f dac ) 2 48 where ftw is a 48 - bit binary number. this method of calculation caus es f car rier values in the second nyquist zone to appear to move to f dac ? f carrier when flipping the fir85 enable bit and not changing the ftw to account for the change in number fo rmat. the intended effect is that a sweep of the nco from 0 hz to f dac ? f dac /2 48 appear s seamless when the fir85 enable bit is set to register 0x111 , bit 0 = 0b1 prior to f carrier /f dac = 0.5. as can be seen from examination, the ftws from 0 to less than f dac /2 mean the same in either case, but they mean different f carrier values from f dac /2 to f dac ? f dac /2 48 . this effect must be considered when constructing ftw values and using the 2 nrz mode. the frequency tuning word is set as shown in table 36. table 36 . nco ftw registers address value description 0x114 ftw[7:0] 8 lsbs of ftw 0x115 ftw[15:8] next 8 bits of ftw 0x116 ftw[23:16] next 8 bits of ftw 0x117 ftw[31:24] next 8 bits of ftw 0x118 ftw[39:32] next 8 bits of ftw 0x119 ftw[47:40] 8 msbs of ftw
data sheet AD9164 rev. a | page 57 of 136 unlike other registers, the ftw registers are not updated immedi - ately upon writing. instead, the ftw registers update on the rising edge of ftw_ load _req (register 0x113 , bit 0 ). afte r an update request, ftw_ load _ack (register 0x113 , bit 1) must be high to acknowledge that the ftw has updated. the sel_sideband bit (register 0x111 , bit 1 = 0b1) is a conven - ience bit that can be set to use the lower sideband modulation result , which is e quivalent to flipping the sign of the f t w. interpolation interpolation nco 1 0 ?1 cos(n + ) sin(n + ) i data q data ftw[47:0] sel_sideband out_i out_q + ? nco_phase_offset [15:0] 14414-108 figure 120 . nco modulator block diagram modulus nco mode (direct digital synthesis (dds)) the main 48 - bit nco can also be used in a dual modulus mode to create fractional frequencies be yond the 48 - bit accuracy. the modulus mode is enabled by programming the modulus_en bit in the datapath_cfg register to 1 (register 0x111 , bit 2 = 0b1). the frequency ratio for the programmable modulus direct digita l synthesis ( dds ) is very similar to tha t of the typical accumulator - based dds. the only difference is that n is not required to be a power of two for the programmable modulus, but can be an arbitrary integer. in practice, h ardware constraints place limits on the range of values for n. as a resu lt, the modulus extends the use of the nco to applications that require exact rational frequenc y synthesis. the underlying function of the programmable modulus technique is to alter the accumulator modulus. implementation of the programmable modulus functi on within the AD9164 is such that the fr action, m/n, is expressi ble per equation 1 . note that the form of the equation implies a compound frequency tuning word with x representing the integer part an d a/b representing the fractional part. 48 2 b a x n m f f dac carrier () ere : x is programmed in reg ister 0x114 to register 0x 119. a is programmed in reg ister 0x12a to register 0x 12f. b is programmed in reg ister 0x124 to register 0x 129. p rogrammable m odulus e x ample consider the case in which f dac = 250 0 mhz and the desired value of f carrier is 25 0 mhz. this scenario synthesizes an output frequency that is not a power of two submultiple of the sample rate, namely f carrier = (1/10) f dac , which is not possible wi th a typical accumulator - based dds. the frequency ratio, f carrier /f dac , leads directly to m and n, which are determined by reducing the fraction (25 0 ,000,000/2 , 50 0 ,000,000) to its lowest terms , that is , m / n = 25 0 ,000,000/2 ,500 ,000,000 = 1/10 therefore, m = 1 and n = 10. after calculation , x = 28147497671065 , a = 3 , and b = 5. pr ogramming these values into the registers for x, a, and b (x is programmed in reg ister 0x114 to register 0x119, b is programmed in register 0x124 to register 0x129, and a is progr ammed in register 0x12a to register 0x12f)) causes the nco to produce an output frequency of exactly 25 0 mhz given a 250 0 mhz sampling clock. for more details, refer to the an - 953 application note on the analog devices , inc., website. nco reset resetting the nco can be useful when determining the start time and phase of the nco. the nco ca n be reset by several differ - ent methods, including a spi write, using the tx_enable pin, or by the sysref sig nal. due to internal timing variations from device to device , these methods achieve an accuracy of 6 dac clock cycles. p rogram register 0x 800 , bits [7:6] to 0b01 to set the nco in phas e discontinuous switching mode via a write to the spi port . then, any ti me the frequency tuning word is updated, the nco phase accumulator reset s and the nco begin s counting at the new ftw. fast frequency hopping (ffh) to support ffh , the AD9164 has several features in th e nco block. there are two implementations of the nco function. the main 48 - bit nco is a general - purpose nco and supports some of the ffh modes, wh ereas the ffh nco is specifically designed to support several different ffh modes. main nco frequency hopping in the main 48- bit nco, the mode of updating the frequency tuning word can be changed from requiring a write to the ftw_load_req bit ( register 0x113 , bit 0 ) to an automatic update mode. in the automatic update mode, the ftw is updated as soon as the chose n ftw word is written. to set the automatic ftw update mode, write the appropriate word to the ftw_req_mode bits (register 0x113 , bits [6:4]), choosing the particular ftw word that causes the automatic update. for example, if relatively coarse frequency ste ps are needed, it may be sufficient to write a single word to the msb byte of the ftw, and therefore the ftw_req_mode bits can be programmed to 110 (register 0x113 , bits [6:4] = 0b110 ) . then, each time the most significant byte, ftw5, is written, the nco ft w is automatically updated. the ftw_req_mode bits can be configured to use any of the ftw words as the auto matic update trigger word. this configura - tion provides convenience when choosing the order in which to program the ftw registers.
AD9164 data sheet rev. a | page 58 of 136 the speed of the spi port write function is guaranteed, and is a minimum of 100 mhz (see table 4 ) . thus, the nco ftw can be updated in as little as 240 ns wi th a one register write in automatic update mode. ffh nco th e ffh nco is i mplemented as the main 48 - bit nco with an a dditional 31, 32 - bit ncos, with an associated bank of 31 ftws . these ftws can be pre loaded into the hopping frequency register bank. an y of the 32 ftws can be selected by a one register write to the hopf_sel bits in the hopf_ctrl registe r (register 0x80 0 , bits [4:0]). th e manner in which the nco transitions to the new frequency is determined by the hopping frequency change mode selection. the ffh nco supports several modes of fast frequency hopping : pha se continuous hopping, phase discontinuous hopping, and phase coherent hopping . the hopping modes are given in table 37. table 37. nco frequency change mode register 0x800, bits[7:6] description 0b00 p hase continuous switch 0b01 phase discontinuous switch (reset nco accumulator) 0b10 phase coherent switch in phase continuous switching, the frequency tuning word of th e nco is updated and the phase accumulator continue s to accumu - late to the new freque ncy. in phase discontinuous mod e, the ftw of the nco is updated and the phase accumulator is reset, making an instantaneous jump to the new frequency. in phase coherent mode, the bank of additional 31 phase accumulators is enabled, one each to shadow each ftw in the hopping frequency register bank. upon enabli ng the phase coherent switching mode (register 0x800 , bits [7:6] = 0b10), all 32 nco phase accumulators begin counting simultaneous ly, and all continue counting regardless of which individual nco outpu t is currently being used in the digital datapath. in this way, the frequency of an individual nco can be chosen and is always phase coherent to time 0. therefore , it is recommended to pre load all ftws, then select the phase coherent switch mode to start t hem at the same time. to conserve power, each of the 31 additional ncos and phase accumulators is enabled only when an ftw is programmed into its register. to power down a particular nco and ph ase accumulato r, program all zeros to the ftw registe r for a gi ven nco. all nco ftws have a default value of 0x0. the main 48 - bit nc o, which is ftw0 in the ffh nco, is enabled by the nco_en bit in the datapath_cfg registe r (register 0x111, bit 6 = 0b1). to ensure that there is no residual power consumption or possibl e residual spurious from one of the 32 - bit ncos after powering it up and then powering it down , the suggested method to power down the additional nco is to first program the ftw to 0x0001, and then program it to 0x0000. this ensures that the phase accumul ator is flushed of resid ual values prior to receiving the all zeros word, which powers down the output but not the accumulator. the accumulator is powered down with the nco_en bit in r egister 0x111 , bit 6. nco only mode the AD9164 is capable of operating in a mode with only the nco enabled. in this mode, a single tone sine wave is generated by the nco engine and sent to the dac output. all of the features discussed in the digit al modulation section are available in the nco only mode. it is not necessary to bring up the jesd204b link in this mode. this mode is a useful option to bring up a transmitter radio signal chain without needing a digital data source, because the device g enerates the nco data internally. this mode can also be used in applications where a sine wave is all that is needed, such as in a local oscillator application . to enable the nco only mode, program the dc_test_en bit in register 0x150, bit 1 = 0b1. then, p rogram a dc value into the two s complement dc test data word in register 0x14e (msb) a nd register 0x14f (lsb). the defau lt value is 0x0000 (zero amplitud e), and a typical value to program is 0x7fff for a full - scale tone. the final step is to program the in terpolation value to 1 bypass mode by selecting interp_mode = 0b0000 in register 0x110 , bits [3:0]. this is necessary because the dc test value is only available in the bypass p ath and is not accessible in the complex data path. wh en dc_test_en = 1, the da ta source of the digital datapath i s the dc test data word. this means that the jesd204b link can be b rought up and data can be successfully transferred to the device over the link, but the data is not presented to the dac when dc_test_en = 1. connection t o the serdes data source is only achieved when dc_test_en = 0. the dc_test_en bit can be set on the fly, but because disabling the mode and switching to the serdes datapath normally requires the lanes and/or interpolation mode to also be set , on the fly se tting or resetting of the dc_test_en bit is normally not practical. inverse sinc the AD9164 provide s a digital inverse sinc filter to compensate the dac roll - off over frequency. the filter is enabled by setting the invs inc_en bit (register 0x111 , bit 7 ) and is dis abled by default. the inverse sinc (sinc ? 1 ) filter is a seven - tap fir filter. figure 121 shows the frequency response of sin(x)/x roll - off, the inverse sinc filter, and the composite response. the composite response has less than 0.05 db pass - band rippl e up to a frequency of 0.4 f dacclk . when 2 nrz mode is enabled, the inverse sinc filter operates to 0.4 f 2 dacclk . to provide the necessary peaking at the upper end of the pass band, the inverse sinc filter shown has an intrinsic insertion loss of abo ut 3.8 db.
data sheet AD9164 rev. a | page 59 of 136 1 0 magnitude (db) ?1 ?2 ?3 ?4 ?5 0 0.05 0.10 0.15 0.20 frequency ( f dac ) 0.25 0.30 0.35 0.45 0.40 0.50 sin(x)/x roll-off sinc ?1 filter response composite response 14414-109 figure 121 . responses of sin (x )/x roll - off, the sinc ?1 filter, and the composite of the two downstream protectio n the AD9164 has several features designed to protect the power amplifier (pa) of the system, as well as other downstream blocks. they cons ist of a control signal from the lmfc s ync logic and a transmit enable function. the protection mechanism in each case is the blanking of data that is passed to the dac decoder. the differences lie in the location in the datapath and slight variations of f unctionality. the jesd204b serial link has several flags and quality measures to indicate the serial link is up and running error free. if any of these measures flags an issue, a signal from the lmfc s ync logic is sent to a mux that stops data from flowing to the dac decoder and replaces it with 0s. there are several transmit enable features, including a tx_ enable r egister that can be used to squelch data at several points in the datapath or configure the tx_enable pin to do likewise. transmit enable th e transmit enabl e feature can be configured either as a spi controlled function or a pin controlled function. it can be used for several different purposes. the spi controlled function has less accurate timing due to its reliance on a microcont roller to pr ogram it; therefore, it is typically used as a preventative measure at power - up or when configuring the device . the spi controlled t x _enable function can be used to zero the input to the digital datapath or to zero the output from the digital datapath, as shown in figure 122 . if the input to the digital datapath is zeroed, any filtering that is selected filter s the 0 signal, causing a gradual ramp - down of energy in the digital datapath. if the digital datapath is b ypassed, as in 1 mode, the data at the input to the dac immediately drop s to zero. the tx_enable pin can be used for more accurate timing when enabling or disabling the dac output. the effect of the tx_enable pin can be configured by the same tx_enable r egister (register 0x03f) as is used for the spi controlled func - tions, and it can be made to have the same effects as the spi controlled function, namely to zero the input to the digital datapath or to zero the output from the digital datapath. in addition , the tx_enable pin can also be configured to ramp down (or up) the full - scale current of the dac. the ramp down reduces the output power of the dac by about 20 db from full scale to the minimum output current. the tx_enable pin can also be programmed to r eset the nco phase accumulator. see table 38 for a description of the settings available for the tx_enable function. table 38 . tx_enable settings register 0x03f setting description bit 7 0 spi control: zero data to the dac 1 spi control: allow data to pass to the dac bit 6 0 spi control: zero data at input to the datapath 1 spi control: allow data to enter the datapath bits[5:4] n/a 1 reserved bit 3 0 use spi writes to reset the nco 2 1 use tx_enable to reset the nco bit 2 0 use spi control to zero data to the dac 1 use tx_enable pin to zero data to the dac bit 1 0 use spi control to zero data at the input to the datapath 1 use tx_enable pin to zero data at input to the datapa th bit 0 0 use spi registers to control the full - scale current 1 use tx_enable pin to control the full - scale current 1 n/a means not applicable. 2 use spi writes to reset the nco if resetting the nco is desired. register 0x800, bits[7:6] determine wh ether the nco is reset. see table 37 for more details. d atapath prbs the datapath prbs can verify the AD9164 datapath receiv es and correctly decod es data. the datapath prbs verifies the jesd204b parameters of the transmitter and receiver match, the lanes of the receiver are mapped appropriately, the lanes are appropriately inverted, and , if necessary, the start - up routine is correctly im plemented. to r un the d a tapath prbs test, complete the following steps: 1. set up the device in the desired operating mode using the start - up s equence. 2. send prbs7 or prbs15 data. 3. write register 0x14b , bit 2 = 0 for prbs7 or 1 for prbs15. 4. write register 0x14b , bits [1:0] = 0b11 to ena ble and reset the prbs test. 5. write register 0x14b , bits [1:0] = 0b01 to enable the prbs test and release reset. 6. wait 500 ms.
AD9164 data sheet rev. a | page 60 of 136 7. check the status of the prbs by checking the irq for the i and q path prbs as described in the d atapath prb s irq section. 8. read register 0x14b , bits [7:6]. bit 6 is 0 if the i channel has any errors. bit 7 is 0 if the q channel has any errors. 9. read register 0x14c to read the error count for the i channel. 10. read register 0x14d to read the error count for the q cha nnel. t h e prbs processes 32 bits at a time, and compares the 32 new bits to the previous set of 32 bits. it detects and reports on ly 1 error in every group of 32 bits; therefore, the error c ount partly d epends on when the errors are seen. for example , s ee the following se quence : ? bits: 32 good ; 31 good, 1 bad; 32 good [2 errors] ? bits: 32 good ; 22 good, 10 bad; 32 good [2 errors] ? bits: 32 good ; 31 good, 1 bad; 31 good, 1 bad; 32 good [3 errors] d atapath prbs irq the prbs fail signals for the i and q path a re available as irq events. use register 0x020 , bits [1:0] to enable the fail signals, and then use register 0x024 , bits [1:0] to read back the status and reset the irq signals. see the interrupt request operation section for more i nformation. main digi t a l pa th da t a from lmfc sync logic 0 0 from reg 0x03f[6] t x _ e nab l e from reg 0x03f[1] 0 from reg 0x03f[7] t x _ e nab l e from reg 0x03f[2] to da c 14414- 1 10 figure 122 . downstream protection block diagram
data sheet AD9164 rev. a | page 61 of 136 interrupt request op eration the AD9164 provide s an interrupt request output signal ( irq ) on ball g1 (8 mm 8 mm csp_bga) or ball g4 ( 11 mm 11 mm csp_bga ) tha t can be used to notify an external host processor of significant device events. on assertion of the interrupt, query the device to determine the precise event that occurred. the irq pin is an open - drain, active low output. pull the irq pin high , external to the device. this pin can be tied to the interrupt pins of other devices with open - drain outputs to wire - or these pins together. figure 123 shows a simpl ified block diagram of how the irq blocks work. if irq_en is low, the interrupt_source signal is set to 0. if irq_en is high, any rising edge of event causes the interrupt _source signal to be set high. if any interrupt_source signal is high, the irq pin is pulled low. interrupt_source can be reset to 0 by either an irq_reset signal or a dev ice_reset signal . depending on the status_mode signal , the event_status bit reads back an event signal o r interrupt_source signal . the AD9164 ha s several interrupt register blocks (irq) that can monitor up to 75 events (depending on device configuration). certain details vary by irq register block as de scribed in table 39 . table 40 shows the source registers of the irq_en, irq_reset, and status_mode signals in figure 123 , as well as the address where event_status is read back. table 39 . irq register block details register block event reported event_status 0x020, 0x024 per chip interrupt_source if irq is enabled ; if not, it is the event s ignal 0x4b8 to 0x4bb; 0x470 to 0x473 per link and lane interrupt_source if irq is enabled ; if not, 0 interrupt service ro utine interrupt request management starts by selecting the set of event flags that require host intervention or mon itoring. enable the events that require host action so that the host is notified when they occur. for events requiring host intervention upon irq activation, run the following routine to clear an interrupt request: 1. read the status of the event flag bits that are being monitored. 2. disable the interrupt by writing 0 to irq_en. 3. read the event source. 4. perform any actions that may be required to clear the cause of the event . in many cases, no specific actions may be required. 5. verify that the e vent source is functioning as expected. 6. clear the interrupt by writing 1 to irq_reset. 7. enable the interrupt by writing 1 to irq_en. irq_en event device_reset event_status interrupt_source irq_en status_mode 1 0 1 0 other interrupt sources irq irq_reset 14414- 11 1 figure 123 . simplified schematic of irq circuitry table 40 . irq register block address of irq signal details register block add ress of irq sign als 1 irq_en irq_reset status_mode 2 event_status 0x020, 0x024 0x020 ; r/w per chip 0x024; w per chip status_mode = irq_en 0x024; r per chip 0x4b8 to 0x4bb 0x4b8, 0x4b9; w per error type 0x4ba, 0x4bb; w per error type n/a, status_mode = 1 0x4 ba , 0x4bb; r per chip 0x470 to 0x473 0x470 to 0x473 ; w per error type 0x470 to 0x473; w per link n/a, status_mode = 1 0x470 to 0x473 ; r per link 1 r is read; w is write; and r/w is read/write. 2 n/a means not applicable.
AD9164 data sheet rev. a | page 62 of 136 applications informa tion h ardware consideratio ns power supply recommendations all the AD9164 supply domains must remain as noise free as possible for the best operation. power supply noise has a frequency component that affect s performance, and is specified in volts rms terms. an lc filter on the output of the power supply is recommended to attenuate the noise, and must be placed as close to the AD9164 as possible. the vdd12_clk supply is the most noise sensitive supply on the device, followed by the vdd25_dac and vneg_n1p2 supplies, which are t he dac output rails. it is highly recommended that the vdd12_clk be supplied by itself with an ultralow noise regulator such as the adm7154 or adp1761 to achieve the best phase noise performance possible. noisier regulators impose phase noise onto the dac output. the vdd12a supply can be connected to the digital dvdd supply with a separate filter network. all of the serdes 1.2 v supplie s can be connected to one regulator with separate filter networks. the iovdd supply can be connected to the vdd 25_ dac supply with a separate filter network, or can be powered from a system controller (for example, a microcontroller) , 1.8 v to 3.3 v supply . the power supply sequencing requirement must be met; therefore, a switch or other solution must be used when connected to the iovdd supply with vdd25_dac. take note of the maximum power consumption numbers given in table 3 to ensure the power supply design can tolerate tempera - ture and ic process variation extremes. the amount of current drawn is dependent on the chosen use cases, and specifications are provided for several use cases to illustrate examples and con tributions from individual blocks, and to assist in calculating the maximu m required current per supply. another consideration for the power supply design is peak current handling capability. the ad91 64 draw s more current in the main digital supply when synthesizing a signal with significant amplitude variations, such as a modulated signal, as compared to when in idle mode or synthesizing a dc signal. therefore, the power supply must be able to supply current quickly to accommodate burst signals such as gsm, tdma, or other signals that have an on/off time domain response. because the amount of current variation depends on the signals used, it is best to perform lab testing first to establish ranges. a typical difference can be several hundred milliamper e s. power sequencing the AD9164 require s power sequencing to avoid damage to the dac. a board design with the AD9164 must include a power sequencer chip, such as the adm1184 , to ensure that the domains power up in the correct order. the adm1184 monitors the level of power domains upon power - up. it sends an enable signal to the next grouping of power domains. when all power domains are powered up, a power - good signal is sent to the system controller to indicate all power su pplies are powered up. the iovdd, vdd12a, vdd12_clk, and dvdd domains must be powered up first. then, the vneg_n1p2, vdd_1p2, pll_clk_vdd12, dvdd_1p2, and sync_vdd_3p3 can be powered up. the vdd25_dac domain must be powered up last. there is no requiremen t for a power - down sequence. power and ground planes solid ground planes are recommended to avoid ground loops and to provide a solid, uninterrupted ground reference for the high speed transmission lines that require controlled impedances. it is recommende d that power planes be stacked between ground layers for high frequency filtering. doing so adds extra filtering and isolation between power supply domains in addition to the decoupling capacitors. do not use segmented power planes as a reference for cont rolled impedances unless the entire length of the controlled impedance trace traverses across only a single segmented plane. these and a dditional guidelines for the topology of high speed transmission lines are described in the jesd204b serial interface inputs (serdin0 to serdin7) section. for some applications, where highest performance and higher output frequencies are required, the choice of pcb materials significantly impacts results. for example, materials su ch as polyimide or materials from the rogers corporation can be used, for example, to improve tolerance to high temperatures and improve performance. rogers 4350 material is used for the top three layers in some of the evaluation board designs: between the top signal layer and the ground layer below it, between the ground layer and an internal signal layer, and between that signal layer and another ground layer. jesd204b serial interface inputs (serdin0 to serdin7) when considering the layout of the jesd2 04b serial interface transmission lines, there are many factors to consider to maintain optimal link performance. among these factors are insertion loss, return loss, signal skew, and the topology of the differential traces.
data sheet AD9164 rev. a | page 63 of 136 insertion loss the jesd204b specification limits the amount of insertion loss allowed in the transmission channel (see figure 95 ). the AD9164 equalization circuitry allows significantly more loss in the channel than is required by the jesd204b specification. it is still important that the designer of the pcb m inimize the amount of insertion loss by adhering to the following guidelines: ? keep the differential traces short by placing the AD9164 as near the transmitting logic device as possible and routing the trace as directly as possible between the devices. ? route the differential pairs on a single plane using a solid ground plane as a reference. it is recommended to route the serdes lanes on the same layer as the AD9164 to avoid vias being used in the serdes lanes. ? use a pcb material with a low dielectric constant (<4) to minimize loss, if possible. when choosing between the stripline and microstrip techniques, keep in mind the following considerations: stripline has less loss (see figure 96 and figure 97 ) and emits less emi, but requires the use of vias that can add complexity to the task of controlling the impedance; whe reas microstrip is easier to implement (if the component placement and density allow routing on the top layer) and eases the task of controlling the impedance. if using the top layer of the pcb is problematic or the advantages of stripline are desirable, f ollow these recommendations: ? minimize the number of vias. ? if possible, use blind vias to eliminate via stub effects and use microvias to minimize via inductance. ? if using standard vias, use the maximum via length to minimize the stub size. for example, on an 8 - layer board, use layer 7 for the stripline pair (see figure 124) . ? for each via pair, place a pair of ground vias adjacent to them to minimize the impedance discontinuity (see figure 124) . layer 1 layer 2 layer 3 layer 4 layer 5 layer 6 layer 7 layer 8 minimize stub effect gnd gnd diff? diff+ y y y add ground vias standard via 14414-100 figure 124 . minimizing stub effect and adding ground vias for differential stripline traces return loss the jesd204b specification limits the amount of return loss allowed in a converter device and a logic d evice, but does not specify return loss for the channel. however, every effort must be made to maintain a continuous impedance on the transmis - sion line between the transmitting logic device and the AD9164 . minimizing the use of vias, or eliminating them all together, reduces one of the primary sources for impedance mismatch es on a transmission line (see the insertion loss section). maintain a solid reference beneath (for microstrip) or above and below (for stripline) the differential traces to ensure continuity in the impedance of th e transmission line. if the stripline tech nique is used, follow the guidelines listed in the insertion loss section to minimize impedance mismatches and stub effects. another primary source for impedance mismatch is at either end of the transmission line, where care must be taken to match the impedance of the termination to that of the transmission line. the AD9164 handle s this internally with a cali brated te rmination scheme for the receiving end of the line. see the interface power - up and input termination section for details on this circuit and the calibration routine. signal skew there are many sources for signal sk ew, but the two sources to consider when laying out a pcb are interconnect skew within a single jesd204b link and skew between multiple jesd204b links. in each case, keeping the channel lengths matched to within 12.5 mm is adequate for operating the jesd20 4b link at speeds of up to 12.5 gbps. this amount of channel length match is equivalent to about 85% ui on the AD9164 evaluation board. managing the interconnect skew within a single link is fairly st raightforward. managing multiple links across multiple devices is more complex. however, follow the 12.5 mm guideline for length matching. the AD9164 can handle more skew than the 85% ui due to the si x pclk cycle buffer i n the jesd204b receiver, but matching the channel lengths as close as possible is still recommended. topology structure the differential serdinx pairs to achieve 50 ? to ground for each half of the pair. stripline vs. microstrip trade - offs are described in the insertion loss section. in either case, it is important to keep these transmission lines separated from potential noise sources such as high speed digital signals and noisy supplies. if u sing stripline differential traces, route them using a coplanar method, with both traces on the same layer. although this method does not offer more noise immunity than the broadside routing method (traces routed on adjacent layers), it is easier to route and manufacture so that the impedance continuity is maintained. an illustration of broadside vs. coplanar is shown in figure 125. tx diff a tx diff a tx diff b tx active tx diff b tx active broadside differentia l tx lines coplanar differentia l tx lines 14414-101 figure 125 . broadside vs. coplanar differential striplin e routing techniques when considering the trace width vs. copper weight and thickness, the speed of the interface must be considered. at multigigabit speeds, the skin effect of the conducting material confines the current flow to the surface. maximize the surface area of the conductor by making the trace width made wider to
AD9164 data sheet rev. a | page 64 of 136 reduce the losses. additionally, loosely couple differential traces to accommodate the wider trace widths. this coupling helps reduce the crosstalk and minimize the impedance mismatch wh en the traces must separate to accommodate components, vias, connectors, or other routing obstacles. tightly coupled vs. loosely coupled differential traces are shown in figure 126. tx diff a tx diff a tx diff b tx diff b tightly coupled differential tx lines loosely coupled differential tx lines 14414-102 figure 126 . tightly coupled vs. loosely coupled differential traces ac coupling capacitors the AD9164 require s that the jesd204b input signals be ac - coupled to the source. these capacitors must be 100 nf and placed as close as possible to the transmitting logic device. to minimiz e the impedance mismatch at the pads, select the package size of the capacitor so that the pad size on the pcb matches the trace width as closely as possible. syncout , sysref, and clk signal s the syncout and sysref signals on the AD9164 are low speed lvds differential signals. use controlled impedance traces routed with 100 ? differential impedance and 50 ? to ground when routing these signals. as with the serdi n0 to serdin7 data pairs, it is important to keep these signals sepa - rated from potential noise sources such as high speed digital signals and noisy supplies. separate the syncout signal from other noisy signals, because noise on the syncout might be interpreted as a request for / k / characters. it is important to keep similar trace lengths for the clk and sysref signals from the clock source to each of the devices on either end of the jesd204b links (see figure 127 ). if using a clock chip that can tightly control the phase of clk and sysref, the trace length matching requirements are greatly reduced. clock source (ad9516-1, adclk925) lane 0 lane 1 lane n ? 1 lane n device clock device clock sysref sysref sysref trace length sysref trace length device clock trace length device clock trace length tx device rx device 14414-103 figure 127 . sysref signal and device clock trace length
data sheet AD9164 rev. a | page 65 of 136 analog interface considerations analog modes of operation the AD9164 uses the quad-switch architecture shown in figure 128. only one pair of switches is enabled during a half-clock cycle, thus requiring each pair to be clocked on alternative clock edges. a key benefit of the quad-switch architecture is that it masks the code dependent glitches that occur in the conventional two-switch dac architecture. v g 1 v ssa ioutp ioutn v g 1v g 2v g 3v g 4 clk clk latches data input v g 2 v g 3 v g 4 14414-112 figure 128. quad-switch architecture in dual-switch architecture, when a switch transition occurs and d 1 and d 2 are in different states, a glitch occurs. however, if d 1 and d 2 happen to be at the same state, the switch transitions and no glitches occur. this code dependent glitching causes an increased amount of distortion in the dac. in quad-switch architecture (no matter what the codes are), there are always two switches that are transitioning at each half-clock cycle, thus eliminating the code dependent glitches but, in the process, creating a constant glitch at 2 f dac . for this reason, a significant clock spur at 2 f dac is evident in the dac output spectrum. input data dacclk_x two-switch dac output four-switch dac output (normal mode) t d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 14414-113 figure 129. two-switch and quad-switch dac waveforms as a consequence of the quad-switch architecture enabling updates on each half-clock cycle, it is possible to operate that dac core at 2 the dac clock rate if new data samples are latched into the dac core on both the rising and falling edge of the dac clock. this notion serves as the basis when operating the AD9164 in either mix-mode or return to zero (rz) mode. in each case, the dac core is presented with new data samples on each clock edge: in rz mode, the rising edge clocks data and the falling edge clocks zero, while in mix-mode; the falling edge sample is simply the complement of the rising edge sample value. when mix-mode is used, the output is effectively chopped at the dac sample rate. this chopping has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the dac sample rate, thus improving the dynamic range of these images. input data dacclk_x four-switch dac output ( f s mix-mode) ?d 6 ?d 7 ?d 8 ?d 9 ?d 10 d 6 d 7 d 8 d 9 d 10 ?d 1 ?d 2 ?d 3 ?d 4 ?d 5 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 1 d 2 d 3 d 4 d 5 t 14414-114 figure 130. mix-mode waveform this ability to change modes provides the user the flexibility to place a carrier anywhere in the first three nyquist zones, depending on the operating mode selected. switching between baseband and mix-mode reshapes the sinc roll-off inherent at the dac output. in baseband mode, the sinc null appears at f dacclk because the same sample latched on the rising clock edge is also latched again on the falling clock edge, thus resulting in the same ubiqui- tous sinc response of a traditional dac. in mix-mode, the complement sample of the rising edge is latched on the falling edge, therefore pushing the sinc null to 2 f dacclk . figure 131 shows the ideal frequency response of the three modes with the sinc roll-off included. frequency (hz) 0fs 1.50fs 1.25fs 1.00fs 0.75fs 0.50fs 0.25fs ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 first nyquist zone second nyquist zone third nyquist zone mix-mode rz mode amplitude (dbfs) normal mode 14414-115 figure 131. sinc roll-off for nrz, rz, and mix-mode operation the quad-switch can be configured via spi (register 0x152, bits[1:0]) to operate in either nrz mode (0b00), rz mode (0b10), or mix-mode (0b01). the AD9164 has an additional frequency response characteristic due to the fir85 filter. this filter samples data on both the rising and falling edges of the dac clock, in essence doubling the input clock frequency. as a result, the nrz (normal) mode roll-off in figure 131 is extended to 2 f dac in figure 131, and follows the mix-mode roll-off due to the zero-order hold at 2 dac clock (see figure 132).
AD9164 data sheet rev. a | page 66 of 136 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 0 1020 2040 3060 4080 5100 6120 7140 8160 9180 10200 power (dbc) frequenc y (mhz) nrz mode 2 nrz mode mix-mode rz mode 14414-193 figure 132 . sinc roll - off with 2 nrz mode added , f dac = 5.1 gsps clock input the ad916 4 contain s a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single - ended clock source. because the input is self biased with a nominal impedance of 90 ? , it is recommended that the clock source be ac - coupled to the clk input pins. t he nominal differential input is 1 v p - p, but the clock receiver can operate with a span that ranges from 250 mv p - p to 2.0 v p - p. better phase noise performance is achieved with a higher clock input level. clk+ t o dac and dl l clk? 1.25v 5k? 5k? 40k? 16 a dut y cycle res t orer cross contro l 14414- 1 16 figure 133 . clock input the quality of the clock source, as well as its interface to the AD9164 clock input, directly impacts ac performance . select the phase noise and spur characteristics of the clock source to meet the target application requirements. phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. it can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 log 10 (f out /f clk ) when the dac clock path contribution is negligible. figure 135 shows a cl ock source based on the adf435 5 low phase noise/jitter pll. the adf4355 can provide output frequencies from 54 mhz up to 6.8 ghz. the clock control r egister s exist at address 0x082 through address 0x084. clk_duty (register 0x082 ) can be used to enable duty cycle correction (bit 7 ), enable duty cycle offset control (bit 6), and set the duty cycle offset (bits[4 :0 ]). the duty cycle offset word is a signe d magnitude word, with bit 4 being the sign bit (1 is negative) and bits [3:0] the magnitude. the duty cycle adjusts across a range of approximately 3 %. recommended settings for this register are listed in the start - up sequence section. the clock input has a register that adjusts the phase of the clk+ and clk ? inputs. this register is located at address 0x07f. the register has a signed magnitude (1 is negative) value that adds capacitance at 20 ff per step to either the clk+ or the clk ? input, according to table 41 . the clk_ phase_ tune register can be used to adjust the clock input phase for better dac image rejection. table 41. clk phase adjust values reg ister 0x07f , bits [5:0] c apacitance at clk+ capacitance at clk ? 000000 0 0 000001 1 20 ff 0 000010 2 20 ff 0 011111 31 20 ff 0 100000 0 0 100001 0 1 20 ff 100010 0 2 20 ff 111111 0 31 20 ff the improvement in performa nce from making these adjustments depends on the accuracy of the balance of the clock input balun and var ies from unit to unit. thus, if a high level of image rejection is required, it is likely that a per unit calibration is necessary. performing this cal ibration can yield significant improvements, as much as 20 db additional rejection of the image due to imbalance. figure 134 shows the results of tuning clock phase, duty cycle (left at default in this case) , and c ross control. the improvement to performance, particular ly at higher frequencies, can b e as much as 20 db. phase 0, cross 6 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 1000 2000 3000 4000 5000 6000 phase 28, cross 10 dac output image power ( f s ? f out ) (dbc) f out (mhz) 14414-221 figure 134 . performance improvement from tuning the clock input
data sheet AD9164 rev. a | page 67 of 136 vco pll adf4355 f ref 2ghz to 6ghz 0dbm 100pf 7.4nh v out v out 7.4nh 100pf AD9164 clk+ clk? output stage 14414-174 figure 135 . possible signal ch ain for clk input shuffle mode the spurious performance of the AD9164 can be improved with a feature called s huffle mode. shuffle mode uses proprietary technology to spread the energy of spurious s ignals across the dac output as random noise. shuffle m ode is enabled by programming register 0x151 , bit 2 = 0b 1. because shuffle is implemented with the msbs, it is more effective when the dac is operated with a small amount of digital back off. the amount of noise rise caused by shuffle m ode is directly related to the power in the affected spurious signals. because the AD9164 has good spurious performance without s huffle active, the penalty of s huffle mode to the noise spectral density is typically about 1 db to 3 db. shuffle mode reduce s spurious performance related to clock and foldback spurs, but does not affect real harmonics of the dac output. examples of the effects of s huffle mode are given in t he typical performance characteristics secti on (see figure 48, figure 49, figure 63, figure 64, and figure 65). dll the clk input goes to a high frequency d ll to ensure robust locking of the dac sample clock to the input clock. the dll is configured and enabl ed as part of the recommended start - up sequence. the d ll control registers are located at register 0x090 through register 0x09b. the dll settings are determined during product characterization and are given in the recommended start - up sequence (see the start - up sequence section). it is not normally necessary to change these values, nor is the product characterization data valid on any settings other than the recom - mended ones. voltage reference the AD9164 output current is set by a combination of digital control bits and the iset reference current, as shown in figure 136 . current scaling ana_full_scale_current [9:0] AD9164 dac i outfs 9.6k ? 1f v ref iset vss iset v bg 1.2v + ? vneg_n1p2 14414- 1 19 figure 136 . voltage reference circuit the reference current is obtained by forcing the band gap voltage across an external 9.6 k? resistor from iset ( ball a15 on the 165- ball csp_bga and ball a12 on the 169- ball csp_bga ) to vneg_n1p2. the 1.2 v nominal band gap voltage (vref) generates a 125 a reference current, iset, in the 9.6 k? resistor, r set . the maximum full - scale current setting is related to the external resistor by the following equation: i outfs = 1.2 v/ r set 320 (ma) note the following constraints when configuring the voltage reference circuit: x both the 9.6 k? resistor and 1 f bypass capacitor are required for proper operation. x adjusting the dac output full - scale current, i outfs , from its default setting of 40 ma must be performed digitally. x the AD9164 is not a multiplying dac . modulation of the reference current, iset, with an ac signal is not supported. x the band gap voltage appearing at the vref pin must be buffered for use with an external circuitry because it has a high output impedance. x an external reference can be used to overdrive the internal reference by connecting it to the vref pin. the i outfs value can be adjusted digitally over an 8 ma to 40 ma range by the ana_ full_scale_current [9:0] bits (registe r 0x042 , bits[7:0] and register 0x041, bits[1:0]). the following equation relates i outfs to the ana_ full_scale_ current [9:0] bits, which can be set from 0 to 1023. i outfs = 32 ma ( ana_full_scale_current [9:0] /1023) + 8 ma no te that the default value of 0x3ff generates 40 ma full scale, and this value is used for most of the characterization presented in this data sheet, unless noted otherwise. temperature sensor the ad916 4 has a band gap temperature sensor for monitoring the temperature changes of the AD9164 . the temperature must be calibrated against a known temperature to remove the device to device variation on th e band gap circ uit that sense s the temperature. to calibrate the temperature, the user must take a reading at a known a mbient temperature for a single point calibration of the AD9164 device. the slop e for the formula is then calculated as
AD9164 data sheet rev. a | page 68 of 136 m = ( t ref + 190)/(( code_ref )/1000) where: t ref is t he calibrated t emperature at which the temp erature sensor is read . code_ref is the readback code at the measured temperature, t ref . to monitor temperature change , t x = t ref + m ( code_x ? code_ref )/1000 where: code_x is the readback code at the unknown temperature, t x . code_ref is the readback code at the calibrated temperature, t ref . to us e th e temperature sensor, enable the sensor by setting register 0x135 to register 0 xa1. the user must write a 1 to register 0x134, bit 0 before reading back the die temperature from register 0x132 (lsb) and register 0x133 (msb). analog outputs equivalent dac output and transfer function the AD9164 provide s complementary current outputs, output+ and output ? , that sink current from an external loa d that is referenced to the 2.5 v vdd25_dac supply. figure 137 shows an equivalent output circuit for the dac. compared to most current output dacs of this type, the outpu ts of the AD9164 consist s of a constant current ( i fixed ), and a peak differential ac current , i c s ( i cs = i csp + i csn ) . these two currents combine to form the i intx currents shown in figure 137 . the internal currents , i intp and i intn , are sent to the output pin and to an input termination resistance equivalent to 100 ? pulled to the vdd 25_dac supply (r int ). this termination serves to divide the output current based on the external termination resistors that are pulled to vdd25_dac. i c s p i outfs = 8m a ? 40m a vdd25_dac vdd25_dac 100? output+ output? 100? i c s n i f i xe d i f i xe d i intn i int p 14414-120 figure 137 . equivalent dac output circuit the example shown i n figure 137 can be modeled as a pair of dc current sources that source a current of i out to each output. this differential ac current source is used to model the signal (that is, a digital code) dependent nature of the dac output. the polarity and signal dependency of this ac current source are related to the digital code (f) by the following equation: f (code) = ( daccode C 32,768 )/ 32,768 (2) w here : ?1 f (code) < + 1. daccode = 0 to 65,535 (decimal). the current that is measured at the output+ and output ? output s is as follows: output+ = ( i fixed (ma) + ( f i outfs )/ f max (ma) ) ( r int /( r int + r load ) ) ( 3 ) output ? = ( i fixed (ma) + ( ( f max ? f ) i outfs )/ f max (ma) ) ( r int /( r int + r load ) ) the i fixed value is about 3.8 ma. it is important to note that the AD9164 output cannot support dc coupling to the external load , and thus must be ac - coupled through ap propriate ly sized capacitors for the chosen operating frequencies. figure 138 shows the output+ vs. dac code transfer function when i outfs is set to 40 ma. dac code 45 output current (ma) 40 35 30 25 20 15 10 5 0 0 16384 32768 49152 65536 14414-121 figure 138 . gain curve for an a_ full_scale_current [9:0] = 1023 , dac offset = 3.8 ma peak dac output power capability the maximum peak power capability of a differential current output dac is dependent on its peak differential ac current, i peak , and the equivalent load resistance it see s. in the case of a 1:1 balun with 10 0 ? differential source termination, the equiva - lent load that is seen by the dac ac current source is 5 0 ?. if the AD9164 is programmed for an i outfs = 4 0 ma, its ideal peak ac current is 20 ma and i ts maximum power, deliv ered to the equivalent load, is 10 (r int /(r int + r load ) = 8 mw (that is, p = i 2 r). because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally. therefore , the output load receives 4 mw, or 6 dbm maximum power. to calculate the rms power delivered to the load, consider the following: x peak to rms of the digital waveform x any digital backoff from digital full scale x dac sinc response and nonideal losses in the external network x dac analog roll - of f due to switch parasitic capacitance and load impedance for example, a sine wave with no digital backoff ideally measures 6 dbm . if a typical balun loss of 1.2 db is included, expect to measure 4.8 dbm of actual power in the region where the sinc response of the dac has negligible influence and analog roll - off
data sheet AD9164 rev. a | page 69 of 136 has not begun . increasing the output power is best accomplished by increasing i outfs . an example of dac output characteristics for several balun and board types is shown in figure 139. 5 0 ?5 output power (dbm) ?10 ?15 ?20 0 1 2 3 f out (ghz) 4 5 6 bal-0006 tc1-1-43x+ tcm1-63ax+ 14414-123 figure 139 . measured dac output response; f dac = 6 gsps output stage configuration the AD9164 is intended to serve high dynamic range applicatio ns that require wide signal reconstruction bandwidth ( such as a docsis cable modem termination system (cmts)) and/or high if/rf signal generation. optimum ac performance can be realized only when the dac output is configured for differen tial (that is, bal anced) operation with its output common - mode voltage b iased to a stable, low noise 2.5 v nominal analog supply (vdd 25_dac ). the output network used to interface to the dac provide s a near 0 ? dc bias path to vdd 25 _dac . any imbalance in the output impedanc e over frequency between the output + and output? pins degrades the distortion performance (mostly even order) and noise performance. component selection and layout are critical in realizing the performance potential of the AD9164 . most applications that require balanced to unbalanced conversion from 10 mhz to 3 ghz can take advantage of several available transformers that offer impedance ratios of both 2:1 and 1:1. figure 140 shows the AD9164 interfacing to the mini - circuits tcm1 - 63ax + and the tc1 - 1 - 43 x + transformer s . 50? 50? l l mini-circuits tcm1-63ax+ tc1-1-43x+ output+ output? c c vdd25_dac 14414-122 figure 140 . recommended transformer for wideband application s wi th upper bandwidths of up to 5 ghz to assist in matching the AD9164 output, a n equiva lent model of the output was developed, and is shown in figure 141. this equivalent model includes all effects from the ideal 40 ma current source in the die to the ball of the csp_ bga package, including parasitic capacitance, trace inductance and resistance, contact resistance of solder bumps, via inductance, and other e ffects . 3.59? 3.59? 470ph 470ph 40m a 179? 1.14pf 248ff output? output+ 14414-124 figure 141 . equivalent circuit model of the dac output a smith chart is provided in figure 142 showing the simulated s11 of the dac output , using the model in figure 141. the plot was taken using the circuit in figure 141 , with a 100 ? differential load instead of the balun. for the measured response of the dac output, see figure 139 .
AD9164 data sheet rev. a | page 70 of 136 0 0 5.0 ?5.0 2.0 1.0 ?1.0 frequency (10mhz to 6ghz) s (1, 1) ?2.0 0.5 ?0.5 0.2 ?0.2 m1 frequenc y = 10mhz s (1, 1) = 0.770/149.556 impedance = z0 (0.140 + j0.267) m2 frequenc y = 100mhz s (1, 1) = 0.227/163.083 impedance = z0 (0.638 + j0.089) m3 frequenc y = 1ghz s (1, 1) = 0.367/?144.722 impedance = z0 (0.499 ? j0.245) m4 frequenc y = 2ghz s (1, 1) = 0.583/?148.777 impedance = z0 (0.282 ? j0.259) m5 frequenc y = 4ghz s (1, 1) = 0.794/?170.517 impedance = z0 (0. 1 16 ? j0.082) m6 frequenc y = 6ghz s (1, 1) = 0.779/168.448 impedance = z0 (0.125 + j0.100) m6 m5 m4 m3 m2 m1 14414-125 figure 142 . simulated smith chart show ing the dac output impedance z o = 100 ?
data sheet AD9164 rev. a | page 71 of 136 s tart - up sequence several steps are required to program the AD9164 to the proper operating state after the device is powered up. this sequence is divided into several steps, and is listed in table 42, table 43 , and table 44 , along with an explanation of the purpose of each step. private registers are reserved but must be written for proper operation. blank cells in table 42 to table 44 mean that the value depends on the result as described in the description column. the AD9164 is calibrated at the factory as part of the automatic test program. the c onfigure dac start - up sequence load s the factory calibration coefficients, as well as configure s some parameters that optimize the performance of the dac and the dac clock dll (see table 42) . run this sequence whenever the dac is powered down or reset. the c onfigure jesd 204b sequenc e configure s the serdes block and then bring s up the links (see table 43 ). first , run the c onfigure dac start - up sequence, then run the c onfigure jesd 204b sequence. follow the c onfigure nco sequence if using the nco (see table 44 ). note that the nco can be used in nco only mode or in conjunction with synthesized data from the serdes data interface. only one mode can be used at a time and this mode is selected in the second step in table 44 . the configure dac start - up sequence is run first, then the c onfigure nco sequence. table 42. configure dac start - up sequence after power -up r/w register value description w 0x000 0x18 configure the device for 4 - wire serial port operation ( o ptional : leave at the default of 3 - wire spi) . w 0x0d2 0x52 reset internal calibration registers ( p rivate) . w 0x0d2 0xd2 clear the r eset bit for the internal calibration registers ( p rivate) . w 0x606 0x02 configure the nonvolatile random access memory (nvram) ( p rivate) . w 0x607 0x00 configure the nvram ( p rivate) . w 0x604 0x01 load the nvram. loads factory calibration factors from the nvram ( p rivate) . r 0x003, 0x004, 0x005, 0x006 n/a 1 ( optional ) r ead chip_type, prod _id [15:0] , prod_grade, and dev_revision from r egister 0x003, register 0x004, register 0x005, and register 0x006 . r 0x604, bit 1 0b1 ( optional ) r ead the b oot loader p ass bit in register 0x604 , bit 1 = 0b1 to indicate a successful boot load . w 0x058 0x03 enable the band gap reference (private) . w 0x0 90 0x1e power up the dac clock dll . w 0x080 0x00 enable the clock r eceiver . w 0x040 0x00 enable the dac bias circuits . w 0x020 0x0f optional . enable the i nterrupts . w 0x09e 0x85 configure dac analog parameters ( p rivate) . w 0x091 0xe9 enable the dac cl ock dll . r 0x092 , bit 0 0b 1 check dll_status ; set register 0x092, bit 0 = 1 to indicate the dac cl oc k dll is locked to the dac clock i nput . w 0x0e8 0x 20 enable calibration factors ( p rivate) . w 0x152 , bits [1:0] configure the dac d ecode mode (0b00 = nrz, 0b01 = mix - mode , or 0b10 = rz) . 1 n/a means not applicable. table 43 . configure jesd 204b start - up sequence r/w register value description w 0x300 0x00 ensure the serdes links are disabled before configuring them. w 0x4b8 0xff enable jesd 204b i nterrupts. w 0x4b9 0x01 enable jesd 204b i nterrupts . w 0x480 0x38 enable serdes e rror counters. w 0x481 0x38 enable serdes e rror counters. w 0x482 0x38 enable serdes e rror counters. w 0x483 0x38 enable serdes e rror counters. w 0x484 0x38 enable serdes e rror cou nters. w 0x485 0x38 enable serdes e rror counters. w 0x486 0x38 enable serdes e rror counters. w 0x487 0x38 enable serdes e rror counters. w 0x1 10 configure number of lanes ( bits [7:4]) and interpolation rate ( bits [3:0]) .
AD9164 data sheet rev. a | page 72 of 136 r/w register value description w 0x111 configure the d atapath options for bit 7 ( invsinc _en ) , bit 6 ( nco_en ) , bit 4 ( f i lt_ b w ), bit 2 ( modulus_en ) , bit 1 ( sel_sideband ) , and bit 0 ( fir85_ f i lt_ en ) . see th e register summary section for details on the options. set the reserved bi ts (bit 5 and bit 3 ) to 0b0. w 0x230 configure the cdr block according to table 19 for both half rate enable and the divider . w 0x289 , bits [1:0] set up the serdes pll divider based on the conditions shown in table 18 . w 0x 084 , bits [5:4] set up the pll reference clock rate based on the conditions shown in table 18. w 0x200 0x00 enable jesd 204b block (disable m aster serdes power - down) . w 0x475 0x09 soft reset the jesd 204b quad - byte deframer . w 0x453 , bit 7 0b1 (optional) enable scrambling on serdes lanes . w 0x458 , bits [ 7: 5] set the subclass type: 0b 00 0 = subclass 0, 0b 00 1 = subclass 1 . w 0x459 , bits [ 7: 5] 0b1 set the jesd 204x version to jesd204b . w 0x45d program the calculated checksum value for lane 0 from values in register 0x450 to register 0x45c . w 0x475 0x01 bring the jesd 204b quad - byte deframer out of reset . w 0x201 , bits [7:0] set any bits to 1 to power down the a ppropriate physical lane. w 0x2 a 7 0x01 (optional) calibrate serdes phy termination bloc k 1 (phy 0, phy 1, phy 6, phy 7 ) . w 0x2ae 0x01 (optional) calibrate serdes phy termination block 2 (phy 2, phy 3, phy 4, phy 5 ) . w 0x29e 0x1f override defaults in t he serdes pll settings ( p rivate) . w 0x206 0x00 reset the cdr . w 0x206 0x01 enable the cdr . w 0x280 0x03 enable the serdes pll . r 0x281 , bit 0 0b1 read back register 0x281 until bit 0 = 1 to indicate the serdes pll is locked . prior to enabling the links , be sure that the jesd204b transmitter is enabled and ready to begin bringing up the link. w 0x300 0x01 enable serdes links ( b egin bringing up the link) . r 0x470 0xff read the cgs status for all lanes . r 0x471 0xff read the f rame s ync status for all la nes . r 0x472 0xff read the g ood c hecksum status for all lanes . r 0x473 0xff read the initial lane sync status for all lanes . w 0x024 0x1f clear the i nterrupts . w 0x4ba 0xff clear the serdes i nterrupts . w 0x4bb 0x01 clear the serdes i nterrupt . table 44 . configure nco sequence r/w register value description w 0x110 0x80 (optional) . perform this write if nco only mode is desired. w 0x111 , bit 6 0b1 configure nco_en (bit 6 ) = 0b1. configure other datapath options for bit 7 ( in v sinc _en ) , bit 4 ( f i lt_ b w ) , bit 2 ( modulus_en ) , bit 1 ( sel_sideband ) , and bit 0 ( fir85_ f i lt_ en ) . see the register summary section for details on the options. set the reserved bits (bit 5 and bit 3 ) to 0b0. w 0x150 , bit 1 configure dc_t est _en bit: 0b0 = nco operation with data interface; 0b1 = nco only mode . w 0x14e write amplitude value for t one amplitude in nco only mode ( bits [15:8] ). w 0x14f write amplitude value for t one amplitude in nco only mode ( bits [ 7:0] ). w 0x113 0x00 ensure the frequency tuning word write request is low . w 0x119 write ftw , bits[47:40] . w 0x118 write f tw , bits[39:32] . w 0x117 write f tw , bits[31:24] . w 0x116 write f tw , bits[23:16] . w 0x115 write f tw , bits[15:8] . w 0x114 w rite f tw , bits[7:0] . w 0x113 0x01 load the ftw to the nco .
data sheet AD9164 rev. a | page 73 of 136 register summary table 45 . register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x000 spi_intfconfa [7:0] softreset_ m lsbfirst_m add rinc_m sdoactive_ m sdoactive addrinc lsbfirst softreset 0x00 r/w 0x001 spi_intfconfb [7:0] singleins cs stall reserved softreset1 softreset0 reserved 0x00 r/w 0x002 spi_devconf [7:0] devstatus custopmode sysopmode 0x00 r/w 0x003 spi_chi ptype [7:0] chip_type 0x00 r 0x004 spi_prodidl [7:0] prod_id[7:0] 0x00 r 0x005 spi_prodidh [7:0] prod_id[15:8] 0x00 r 0x006 spi_chipgrade [7:0] prod_grade dev_revision 0x00 r 0x020 irq_enable [7:0] reserved en_sysref_ jitter en_data_ ready en_lane_fifo en_prbsq en_prbsi 0x00 r/w 0x024 irq_status [7:0] reserved irq_sysref_ jitter irq_data_ ready irq_lane_ fifo irq_prbsq irq_prbsi 0x00 r/w 0x031 sync_lmfc_ delay_frame [7:0] reserved sync_lmfc_delay_set_frm 0x00 r/w 0x032 sync_lmfc_ delay0 [7:0] sync_lmf c_delay_set[7:0] 0x00 r/w 0x033 sync_lmfc_ delay1 [7:0] reserved sync_lmfc_delay_set[11:8] 0x00 r/w 0x034 sync_lmfc_ stat0 [7:0] sync_lmfc_delay_stat[7:0] 0x00 r/w 0x035 sync_lmfc_ stat1 [7:0] reserved sync_lmfc_delay_stat[11:8] 0x00 r/w 0x036 sysref_c ount [7:0] sysref_count 0x00 r/w 0x037 sysref_phase0 [7:0] sysref_phase[7:0] 0x00 r/w 0x038 sysref_phase1 [7:0] reserved sysref_phase[11:8] 0x00 r/w 0x039 sysref_jitter_ window [7:0] reserved sysref_jitter_window 0x00 r/w 0x03a sync_ctrl [7:0] reserved sync_mode 0x00 r/w 0x03f tx_enable [7:0] spi_ datapath_ post spi_ datapath_ pre reserved txen_nco_ reset txen_ datapath_ post txen_ datapath_ pre txen_dac_fsc 0xc0 r/w 0x040 ana_dac_bias_ pd [7:0] reserved ana_dac_ bias_pd1 ana_dac_bias_ pd0 0x03 r/w 0x 041 ana_fsc0 [7:0] reserved ana_full_scale_current[1:0] 0x03 r/w 0x042 ana_fsc1 [7:0] ana_full_scale_current[9:2] 0xff r/w 0x07f clk_phase_tune [7:0] reserved clk_phase_tune 0x00 r/w 0x080 clk_pd [7:0] reserved dacclk_pd 0x01 r/w 0x082 clk_duty [7:0] c lk_duty_ en clk_duty_ offset_en clk_duty_ boost_en clk_duty_prg 0x80 r/w 0x083 clk_crs_ctrl [7:0] clk_crs_en reserved clk_crs_adj 0x80 r/w 0x084 pll_ref_clk_pd [7:0] reserved pll_ref_clk_rate reserved pll_ref_clk_pd 0x00 r/w 0x088 sysref_ctrl0 [7:0] res erved hys_on sysref_rise hys_cntrl[9:8] 0x00 r/w 0x089 sysref_ctrl1 [7:0] hys_cntrl[7:0] 0x00 r/w 0x090 dll_pd [7:0] reserved dll_fine_ dc_en dll_fine_ xc_en dll_coarse_ dc_en dll_coarse_ xc_en dll_clk_pd 0x1f r/w 0x091 dll_ctrl [7:0] dll_track_ err dll _search_ err dll_slope dll_search dll_mode dll_enable 0xf0 r/w 0x092 dll_status [7:0] reserved dll_fail dll_lost dll_locked 0x00 r/w 0x093 dll_gb [7:0] reserved dll_guard 0x00 r/w 0x094 dll_coarse [7:0] reserved dll_coarse 0x00 r/w 0x095 dll_fine [7:0] dll_fine 0x80 r/w
AD9164 data sheet rev. a | page 74 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x096 dll_phase [7:0] reserved dll_phs 0x08 r/w 0x097 dll_bw [7:0] reserved dll_filt_bw dll_weight 0x00 r/w 0x098 dll_read [7:0] reserved dll_read 0x00 r/w 0x099 dll_coarse_rb [7:0] reserved dll_coarse_rb 0x00 r 0x09a dll_fine_rb [7: 0] dll_fine_rb 0x00 r 0x09b dll_phase_rb [7:0] reserved dll_phs_rb 0x00 r 0x09d dig_clk_invert [7:0] reserved inv_dig_clk dig_clk_dc_ en dig_clk_xc_en 0x03 r/w 0x0a0 dll_clk_debug [7:0] dll_test_en reserved dll_test_div 0x00 r/w 0x110 interp_mode [7:0] jesd_lanes interp_mode 0x81 r/w 0x111 datapath_cfg [7:0] invsinc_en nco_en reserved filt_bw reserved modulus_en sel_sideband fir85_filt_en 0x00 r/w 0x113 ftw_update [7:0] reserved ftw_req_mode reserved ftw_load_ sysref ftw_load_ ack ftw_load_req 0x00 r/ w 0x114 ftw0 [7:0] ftw[7:0] 0x00 r/w 0x115 ftw1 [7:0] ftw[15:8] 0x00 r/w 0x116 ftw2 [7:0] ftw[23:16] 0x00 r/w 0x117 ftw3 [7:0] ftw[31:24] 0x00 r/w 0x118 ftw4 [7:0] ftw[39:32] 0x00 r/w 0x119 ftw5 [7:0] ftw[47:40] 0x00 r/w 0x11c phase_offset0 [7:0] nc o_phase_offset[7:0] 0x00 r/w 0x11d phase_offset1 [7:0] nco_phase_offset[15:8] 0x00 r/w 0x124 acc_modulus0 [7:0] acc_modulus[7:0] 0x00 r/w 0x125 acc_modulus1 [7:0] acc_modulus[15:8] 0x00 r/w 0x126 acc_modulus2 [7:0] acc_modulus[23:16] 0x00 r/w 0x127 ac c_modulus3 [7:0] acc_modulus[31:24] 0x00 r/w 0x128 acc_modulus4 [7:0] acc_modulus[39:32] 0x00 r/w 0x129 acc_modulus5 [7:0] acc_modulus[47:40] 0x00 r/w 0x12a acc_delta0 [7:0] acc_delta[7:0] 0x00 r/w 0x12b acc_delta1 [7:0] acc_delta[15:8] 0x00 r/w 0x12c acc_delta2 [7:0] acc_delta[23:16] 0x00 r/w 0x12d acc_delta3 [7:0] acc_delta[31:24] 0x00 r/w 0x12e acc_delta4 [7:0] acc_delta[39:32] 0x00 r/w 0x12f acc_delta5 [7:0] acc_delta[47:40] 0x00 r/w 0x132 temp_sens_lsb [7:0] temp_sens_out[7:0] r 0x133 temp_s ens_msb [7:0] temp_sens_out[15:8] r 0x134 temp_sens_ update [7:0] reserved temp_sens_ update 0x00 r/w 0x135 temp_sens_ctrl [7:0] temp_sens_ fast reserved temp_sens_ enable r/w 0x14b prbs [7:0] prbs_good_ q prbs_good_i reserved prbs_inv_q prbs_inv_i prb s_mode prbs_reset prbs_en 0x10 r/w 0x14c prbs_error_i [7:0] prbs_count_i 0x00 r 0x14d prbs_error_q [7:0] prbs_count_q 0x00 r 0x14e test_dc_data1 [7:0] dc_test_data[15:8] 0x00 r/w 0x14f test_dc_data0 [7:0] dc_test_data[7:0] 0x00 r/w 0x150 dig_test [7:0 ] reserved dc_test_en reserved 0x00 r/w 0x151 decode_ctrl [7:0] reserved shuffle reserved 0x01 r/w 0x152 decode_mode [7:0] reserved decode_mode 0x00 r/w 0x1df spi_strength [7:0] reserved spidrv 0x0f r/w 0x200 master_pd [7:0] reserved spi_pd_master 0x01 r/w 0x201 phy_pd [7:0] spi_pd_phy 0x00 r/w
data sheet AD9164 rev. a | page 75 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x203 generic_pd [7:0] reserved spi_sync1_pd reserved 0x00 r/w 0x206 cdr_reset [7:0] reserved spi_cdr_ reset 0x01 r/w 0x230 cdr_operating_ mode_reg_0 [7:0] reserved spi_ enhalfrate reserved sp i_division_rate reserved 0x28 r/w 0x250 eq_config_phy_ 0_1 [7:0] spi_eq_config1 spi_eq_config0 0x88 r/w 0x251 eq_config_phy_ 2_3 [7:0] spi_eq_config3 spi_eq_config2 0x88 r/w 0x252 eq_config_phy_ 4_5 [7:0] spi_eq_config5 spi_eq_config4 0x88 r/w 0x253 eq_co nfig_phy_ 6_7 [7:0] spi_eq_config7 spi_eq_config6 0x88 r/w 0x268 eq_bias_reg [7:0] eq_power_mode reserved 0x62 r/w 0x280 synth_enable_ cntrl [7:0] reserved spi_recal_ synth reserved spi_enable_ synth 0x00 r/w 0x281 pll_status [7:0] reserved spi_cp_ over_ range_ high_rb spi_cp_ over_ range_ low_rb spi_cp_ cal_valid_ rb reserved spi_pll_lock_rb 0x00 r 0x289 ref_clk_ divider_ldo [7:0] reserved serdes_pll_div_factor 0x04 r/w 0x2a7 term_blk1_ ctrlreg0 [7:0] reserved spi_i_tune_r_ cal_termblk1 0x00 r/w 0x2a8 term_blk1_ ctrlreg1 [7:0] spi_i_serializer_rtrim_termblk1 0x00 r/w 0x2ac term_blk1_rd_ reg0 [7:0] reserved spi_o_rcal_code_termblk1 0x00 r 0x2ae term_blk2_ ctrlreg0 [7:0] reserved spi_i_tune_r_ cal_termblk2 0x00 r/w 0x2af term_blk2_ ctrlreg1 [7:0] spi_i _serializer_rtrim_termblk2 0x00 r/w 0x2b3 term_blk2_rd_ reg0 [7:0] reserved spi_o_rcal_code_termblk2 0x00 r 0x2bb term_offset_0 [7:0] reserved term_offset_0 0x00 r/w 0x2bc term_offset_1 [7:0] reserved term_offset_1 0x00 r/w 0x2bd term_offset_2 [7:0] re served term_offset_2 0x00 r/w 0x2be term_offset_3 [7:0] reserved term_offset_3 0x00 r/w 0x2bf term_offset_4 [7:0] reserved term_offset_4 0x00 r/w 0x2c0 term_offset_5 [7:0] reserved term_offset_5 0x00 r/w 0x2c1 term_offset_6 [7:0] reserved term_offset_6 0x00 r/w 0x2c2 term_offset_7 [7:0] reserved term_offset_7 0x00 r/w 0x300 general_jrx_ ctrl_0 [7:0] reserved checksum_ mode reserved link_en 0x00 r/w 0x302 dyn_link_ latency_0 [7:0] reserved dyn_link_latency_0 0x00 r 0x304 lmfc_delay_0 [7:0] reserved l mfc_delay_0 0x00 r/w 0x306 lmfc_var_0 [7:0] reserved lmfc_var_0 0x1f r/w 0x308 xbar_ln_0_1 [7:0] reserved src_lane1 src_lane0 0x08 r/w 0x309 xbar_ln_2_3 [7:0] reserved src_lane3 src_lane2 0x1a r/w 0x30a xbar_ln_4_5 [7:0] reserved src_lane5 src_lane4 0x 2c r/w 0x30b xbar_ln_6_7 [7:0] reserved src_lane7 src_lane6 0x3e r/w 0x30c fifo_status_ reg_0 [7:0] lane_fifo_full 0x00 r 0x30d fifo_status_ reg_1 [7:0] lane_fifo_empty 0x00 r 0x311 sync _gen_0 [7:0] reserved eomf_mask_0 reserved eof_m ask_0 0x00 r/w
AD9164 data sheet rev. a | page 76 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x312 sync _gen_1 [7:0] sync _err_dur sync _syncreq_dur 0x00 r/w 0x313 sync _gen_3 [7:0] lmfc_period 0x00 r 0x315 phy_prbs_test_ en [7:0] phy_test_en 0x00 r/w 0x316 phy_ prbs_test_ ctrl [7:0] reserved phy_src_err_cnt phy_prbs_pat_sel phy_test_ start phy_test_reset 0x00 r/w 0x317 phy_prbs_test_ threshold_ lobits [7:0] phy_prbs_threshold_lobits 0x00 r/w 0x318 phy_prbs_test_ threshold_ midbits [7:0] phy_prbs_threshold_midbit s 0x00 r/w 0x319 phy_prbs_test_ threshold_ hibits [7:0] phy_prbs_threshold_hibits 0x00 r/w 0x31a phy_prbs_test_ errcnt_lobits [7:0] phy_prbs_err_cnt_lobits 0x00 r 0x31b phy_prbs_test_ errcnt_midbits [7:0] phy_prbs_err_cnt_midbits 0x00 r 0x31c phy_prbs_ test_ errcnt_hibits [7:0] phy_prbs_err_cnt_hibits 0x00 r 0x31d phy_prbs_test_ status [7:0] phy_prbs_pass 0xff r 0x31e phy_data_ snapshot_ctrl [7:0] reserved phy_grab_lane_sel phy_grab_ mode phy_grab_data 0x00 r/w 0x31f phy_snapshot_ data_byte0 [7:0] phy_ snapshot_data_byte0 0x00 r 0x320 phy_snapshot_ data_byte1 [7:0] phy_snapshot_data_byte1 0x00 r 0x321 phy_snapshot_ data_byte2 [7:0] phy_snapshot_data_byte2 0x00 r 0x322 phy_snapshot_ data_byte3 [7:0] phy_snapshot_data_byte3 0x00 r 0x323 phy_snapshot_ data_ byte4 [7:0] phy_snapshot_data_byte4 0x00 r 0x32c short_tpl_ test_0 [7:0] short_tpl_sp_sel short_tpl_m_sel short_tpl_ test_reset short_tpl_test_ en 0x00 r/w 0x32d short_tpl_ test_1 [7:0] short_tpl_ref_sp_lsb 0x00 r/w 0x32e short_tpl_ test_2 [7:0] short_tp l_ref_sp_msb 0x00 r/w 0x32f short_tpl_ test_3 [7:0] reserved short_tpl_fail 0x00 r 0x334 jesd_bit_ inverse_ctrl [7:0] jesd_bit_inverse 0x00 r/w 0x400 did_reg [7:0] did_rd 0x00 r 0x401 bid_reg [7:0] bid_rd 0x00 r 0x402 lid0_reg [7:0] reserved adjdir_rd phadj_rd ll_lid0 0x00 r 0x403 scr_l_reg [7:0] scr_rd reserved l_rd 0x00 r 0x404 f_reg [7:0] f_rd 0x00 r 0x405 k_reg [7:0] reserved k_rd 0x00 r 0x406 m_reg [7:0] m_rd 0x00 r 0x407 cs_n_reg [7:0] cs_rd reserved n_rd 0x00 r 0x408 np_reg [7:0] subclassv _rd np_rd 0x00 r 0x409 s_reg [7:0] jesdv_rd s_rd 0x00 r 0x40a hd_cf_reg [7:0] hd_rd reserved cf_rd 0x00 r 0x40b res1_reg [7:0] res1_rd 0x00 r 0x40c res2_reg [7:0] res2_rd 0x00 r
data sheet AD9164 rev. a | page 77 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x40d checksum0_reg [7:0] ll_fchk0 0x00 r 0x40e compsum0_reg [7:0] ll_fc mp0 0x00 r 0x412 lid1_reg [7:0] reserved ll_lid1 0x00 r 0x415 checksum1_reg [7:0] ll_fchk1 0x00 r 0x416 compsum1_reg [7:0] ll_fcmp1 0x00 r 0x41a lid2_reg [7:0] reserved ll_lid2 0x00 r 0x41d checksum2_reg [7:0] ll_fchk2 0x00 r 0x41e compsum2_reg [7:0] ll_fcmp2 0x00 r 0x422 lid3_reg [7:0] reserved ll_lid3 0x00 r 0x425 checksum3_reg [7:0] ll_fchk3 0x00 r 0x426 compsum3_reg [7:0] ll_fcmp3 0x00 r 0x42a lid4_reg [7:0] reserved ll_lid4 0x00 r 0x42d checksum4_reg [7:0] ll_fchk4 0x00 r 0x42e compsum4_reg [7:0] ll_fcmp4 0x00 r 0x432 lid5_reg [7:0] reserved ll_lid5 0x00 r 0x435 checksum5_reg [7:0] ll_fchk5 0x00 r 0x436 compsum5_reg [7:0] ll_fcmp5 0x00 r 0x43a lid6_reg [7:0] reserved ll_lid6 0x00 r 0x43d checksum6_reg [7:0] ll_fchk6 0x00 r 0x43e compsu m6_reg [7:0] ll_fcmp6 0x00 r 0x442 lid7_reg [7:0] reserved ll_lid7 0x00 r 0x445 checksum7_reg [7:0] ll_fchk7 0x00 r 0x446 compsum7_reg [7:0] ll_fcmp7 0x00 r 0x450 ils_did [7:0] did 0x00 r/w 0x451 ils_bid [7:0] bid 0x00 r/w 0x452 ils_lid0 [7:0] reserv ed adjdir phadj lid0 0x00 r/w 0x453 ils_scr_l [7:0] scr reserved l 0x87 r/w 0x454 ils_f [7:0] f 0x00 r 0x455 ils_k [7:0] reserved k 0x1f r/w 0x456 ils_m [7:0] m 0x01 r 0x457 ils_cs_n [7:0] cs reserved n 0x0f r 0x458 ils_np [7:0] subclassv np 0x0f r/w 0x459 ils_s [7:0] jesdv s 0x01 r/w 0x45a ils_hd_cf [7:0] hd reserved cf 0x80 r 0x45b ils_res1 [7:0] res1 0x00 r/w 0x45c ils_res2 [7:0] res2 0x00 r/w 0x45d ils_checksum [7:0] fchk0 0x00 r/w 0x46c lane_deskew [7:0] ild7 ils6 ild5 ild4 ild3 ild2 ild1 i ld0 0x00 r 0x46d bad_disparity [7:0] bde7 bde6 bde5 bde4 bde3 bde2 bde1 bde0 0x00 r 0x46e not_in_table [7:0] nit7 nit6 nit5 nit4 nit3 nit2 nit1 nit0 0x00 r 0x46f unexpected_ kchar [7:0] uek7 uek6 uek5 uek4 uek3 uek2 uek1 uek0 0x00 r 0x470 code_grp_sync [7:0] cgs7 cgs6 cgs5 cgs4 cgs3 cgs2 cgs1 cgs0 0x00 r 0x471 frame_sync [7:0] fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 0x00 r 0x472 good_ checksum [7:0] cks7 cks6 cks5 cks4 cks3 cks2 cks1 cks0 0x00 r 0x473 init_lane_sync [7:0] ils7 ils6 ils5 ils4 ils3 ils2 ils1 i ls0 0x00 r 0x475 ctrlreg0 [7:0] rx_dis char_repl_ dis reserved softrst forcesyncreq reserved repl_frm_ena 0x01 r/w 0x476 ctrlreg1 [7:0] reserved qual_rderr del_scr cgs_sel no_ilas fchk_n 0x14 r/w
AD9164 data sheet rev. a | page 78 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x477 ctrlreg2 [7:0] ils_mode reserved repdatatest quetes terr ar_ecntr reserved 0x00 r/w 0x478 kval [7:0] ksync 0x01 r/w 0x47c errorthres [7:0] eth 0xff r/w 0x47d sync_assert_ mask [7:0] reserved sync_assert_mask 0x07 r/w 0x480 ecnt_ctrl0 [7:0] reserved ecnt_ena0 ecnt_rst0 0x3f r/w 0x481 ecnt_ctrl1 [7:0] re served ecnt_ena1 ecnt_rst1 0x3f r/w 0x482 ecnt_ctrl2 [7:0] reserved ecnt_ena2 ecnt_rst2 0x3f r/w 0x483 ecnt_ctrl3 [7:0] reserved ecnt_ena3 ecnt_rst3 0x3f r/w 0x484 ecnt_ctrl4 [7:0] reserved ecnt_ena4 ecnt_rst4 0x3f r/w 0x485 ecnt_ctrl5 [7:0] reserved e cnt_ena5 ecnt_rst5 0x3f r/w 0x486 ecnt_ctrl6 [7:0] reserved ecnt_ena6 ecnt_rst6 0x3f r/w 0x487 ecnt_ctrl7 [7:0] reserved ecnt_ena7 ecnt_rst7 0x3f r/w 0x488 ecnt_tch0 [7:0] reserved ecnt_tch0 0x07 r/w 0x489 ecnt_tch1 [7:0] reserved ecnt_tch1 0x07 r/w 0 x48a ecnt_tch2 [7:0] reserved ecnt_tch2 0x07 r/w 0x48b ecnt_tch3 [7:0] reserved ecnt_tch3 0x07 r/w 0x48c ecnt_tch4 [7:0] reserved ecnt_tch4 0x07 r/w 0x48d ecnt_tch5 [7:0] reserved ecnt_tch5 0x07 r/w 0x48e ecnt_tch6 [7:0] reserved ecnt_tch6 0x07 r/w 0x 48f ecnt_tch7 [7:0] reserved ecnt_tch7 0x07 r/w 0x490 ecnt_stat0 [7:0] reserved lane_ena0 ecnt_tcr0 0x00 r 0x491 ecnt_stat1 [7:0] reserved lane_ena1 ecnt_tcr1 0x00 r 0x492 ecnt_stat2 [7:0] reserved lane_ena2 ecnt_tcr2 0x00 r 0x493 ecnt_stat3 [7:0] rese rved lane_ena3 ecnt_tcr3 0x00 r 0x494 ecnt_stat4 [7:0] reserved lane_ena4 ecnt_tcr4 0x00 r 0x495 ecnt_stat5 [7:0] reserved lane_ena5 ecnt_tcr5 0x00 r 0x496 ecnt_stat6 [7:0] reserved lane_ena6 ecnt_tcr6 0x00 r 0x497 ecnt_stat7 [7:0] reserved lane_ena7 e cnt_tcr7 0x00 r 0x4b0 link_status0 [7:0] bde0 nit0 uek0 ild0 ils0 cks0 fs0 cgs0 0x00 r 0x4b1 link_status1 [7:0] bde1 nit1 uek1 ild1 ils1 cks1 fs1 cgs1 0x00 r 0x4b2 link_status2 [7:0] bde2 nit2 uek2 ild2 ils2 cks2 fs2 cgs2 0x00 r 0x4b3 link_status3 [7:0 ] bde3 nit3 uek3 ild3 ils3 cks3 fs3 cgs3 0x00 r 0x4b4 link_status4 [7:0] bde4 nit4 uek4 ild4 ils4 cks4 fs4 cgs4 0x00 r 0x4b5 link_status5 [7:0] bde5 nit5 uek5 ild5 ils5 cks5 fs5 cgs5 0x00 r 0x4b6 link_status6 [7:0] bde6 nit6 uek6 ild6 ils6 cks6 fs6 cgs6 0x00 r 0x4b7 link_status7 [7:0] bde7 nit7 uek7 ild7 ils7 cks7 fs7 cgs7 0x00 r 0x4b8 jesd_irq_ enablea [7:0] en_bde en_nit en_uek en_ild en_ils en_cks en_fs en_cgs 0x00 r/w 0x4b9 jesd_irq_ enableb [7:0] reserved en_ilas 0x00 r/w 0x4ba jesd_irq_ statusa [7:0] irq_bde irq_nit irq_uek irq_ild irq_ils irq_cks irq_fs irq_cgs 0x00 r/w 0x4bb jesd_irq_ statusb [7:0] reserved irq_ilas 0x00 r/w 0x800 hopf_ctrl [7:0] hopf_mode reserved hopf_sel 0x00 r/w 0x806 hopf_ftw1_0 [7:0] hopf_ftw1[7:0] 0x00 r/w 0x807 hop f_ftw1_1 [7:0] hopf_ftw1[15:8] 0x00 r/w 0x808 hopf_ftw1_2 [7:0] hopf_ftw1[23:16] 0x00 r/w 0x809 hopf_ftw1_3 [7:0] hopf_ftw1[31:24] 0x00 r/w
data sheet AD9164 rev. a | page 79 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x80a hopf_ftw2_0 [7:0] hopf_ftw2[7:0] 0x00 r/w 0x80b hopf_ftw2_1 [7:0] hopf_ftw2[15:8] 0x00 r/w 0x80c hopf_ftw 2_2 [7:0] hopf_ftw2[23:16] 0x00 r/w 0x80d hopf_ftw2_3 [7:0] hopf_ftw2[31:24] 0x00 r/w 0x80e hopf_ftw3_0 [7:0] hopf_ftw3[7:0] 0x00 r/w 0x80f hopf_ftw3_1 [7:0] hopf_ftw3[15:8] 0x00 r/w 0x810 hopf_ftw3_2 [7:0] hopf_ftw3[23:16] 0x00 r/w 0x811 hopf_ftw3_3 [7:0] hopf_ftw3[31:24] 0x00 r/w 0x812 hopf_ftw4_0 [7:0] hopf_ftw4[7:0] 0x00 r/w 0x813 hopf_ftw4_1 [7:0] hopf_ftw4[15:8] 0x00 r/w 0x814 hopf_ftw4_2 [7:0] hopf_ftw4[23:16] 0x00 r/w 0x815 hopf_ftw4_3 [7:0] hopf_ftw4[31:24] 0x00 r/w 0x816 hopf_ftw5_0 [7:0 ] hopf_ftw5[7:0] 0x00 r/w 0x817 hopf_ftw5_1 [7:0] hopf_ftw5[15:8] 0x00 r/w 0x818 hopf_ftw5_2 [7:0] hopf_ftw5[23:16] 0x00 r/w 0x819 hopf_ftw5_3 [7:0] hopf_ftw5[31:24] 0x00 r/w 0x81a hopf_ftw6_0 [7:0] hopf_ftw6[7:0] 0x00 r/w 0x81b hopf_ftw6_1 [7:0] hopf _ftw6[15:8] 0x00 r/w 0x81c hopf_ftw6_2 [7:0] hopf_ftw6[23:16] 0x00 r/w 0x81d hopf_ftw6_3 [7:0] hopf_ftw6[31:24] 0x00 r/w 0x81e hopf_ftw7_0 [7:0] hopf_ftw7[7:0] 0x00 r/w 0x81f hopf_ftw7_1 [7:0] hopf_ftw7[15:8] 0x00 r/w 0x820 hopf_ftw7_2 [7:0] hopf_ftw7 [23:16] 0x00 r/w 0x821 hopf_ftw7_3 [7:0] hopf_ftw7[31:24] 0x00 r/w 0x822 hopf_ftw8_0 [7:0] hopf_ftw8[7:0] 0x00 r/w 0x823 hopf_ftw8_1 [7:0] hopf_ftw8[15:8] 0x00 r/w 0x824 hopf_ftw8_2 [7:0] hopf_ftw8[23:16] 0x00 r/w 0x825 hopf_ftw8_3 [7:0] hopf_ftw8[31: 24] 0x00 r/w 0x826 hopf_ftw9_0 [7:0] hopf_ftw9[7:0] 0x00 r/w 0x827 hopf_ftw9_1 [7:0] hopf_ftw9[15:8] 0x00 r/w 0x828 hopf_ftw9_2 [7:0] hopf_ftw9[23:16] 0x00 r/w 0x829 hopf_ftw9_3 [7:0] hopf_ftw9[31:24] 0x00 r/w 0x82a hopf_ftw10_0 [7:0] hopf_ftw10[7:0] 0x00 r/w 0x82b hopf_ftw10_1 [7:0] hopf_ftw10[15:8] 0x00 r/w 0x82c hopf_ftw10_2 [7:0] hopf_ftw10[23:16] 0x00 r/w 0x82d hopf_ftw10_3 [7:0] hopf_ftw10[31:24] 0x00 r/w 0x82e hopf_ftw11_0 [7:0] hopf_ftw11[7:0] 0x00 r/w 0x82f hopf_ftw11_1 [7:0] hopf_ftw11[1 5:8] 0x00 r/w 0x830 hopf_ftw11_2 [7:0] hopf_ftw11[23:16] 0x00 r/w 0x831 hopf_ftw11_3 [7:0] hopf_ftw11[31:24] 0x00 r/w 0x832 hopf_ftw12_0 [7:0] hopf_ftw12[7:0] 0x00 r/w 0x833 hopf_ftw12_1 [7:0] hopf_ftw12[15:8] 0x00 r/w 0x834 hopf_ftw12_2 [7:0] hopf_ft w12[23:16] 0x00 r/w 0x835 hopf_ftw12_3 [7:0] hopf_ftw12[31:24] 0x00 r/w 0x836 hopf_ftw13_0 [7:0] hopf_ftw13[7:0] 0x00 r/w 0x837 hopf_ftw13_1 [7:0] hopf_ftw13[15:8] 0x00 r/w 0x838 hopf_ftw13_2 [7:0] hopf_ftw13[23:16] 0x00 r/w 0x839 hopf_ftw13_3 [7:0] h opf_ftw13[31:24] 0x00 r/w
AD9164 data sheet rev. a | page 80 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x83a hopf_ftw14_0 [7:0] hopf_ftw14[7:0] 0x00 r/w 0x83b hopf_ftw14_1 [7:0] hopf_ftw14[15:8] 0x00 r/w 0x83c hopf_ftw14_2 [7:0] hopf_ftw14[23:16] 0x00 r/w 0x83d hopf_ftw14_3 [7:0] hopf_ftw14[31:24] 0x00 r/w 0x83e hopf_ftw15_0 [ 7:0] hopf_ftw15[7:0] 0x00 r/w 0x83f hopf_ftw15_1 [7:0] hopf_ftw15[15:8] 0x00 r/w 0x840 hopf_ftw15_2 [7:0] hopf_ftw15[23:16] 0x00 r/w 0x841 hopf_ftw15_3 [7:0] hopf_ftw15[31:24] 0x00 r/w 0x842 hopf_ftw16_0 [7:0] hopf_ftw16[7:0] 0x00 r/w 0x843 hopf_ftw16 _1 [7:0] hopf_ftw16[15:8] 0x00 r/w 0x844 hopf_ftw16_2 [7:0] hopf_ftw16[23:16] 0x00 r/w 0x845 hopf_ftw16_3 [7:0] hopf_ftw16[31:24] 0x00 r/w 0x846 hopf_ftw17_0 [7:0] hopf_ftw17[7:0] 0x00 r/w 0x847 hopf_ftw17_1 [7:0] hopf_ftw17[15:8] 0x00 r/w 0x848 hopf_ ftw17_2 [7:0] hopf_ftw17[23:16] 0x00 r/w 0x849 hopf_ftw17_3 [7:0] hopf_ftw17[31:24] 0x00 r/w 0x84a hopf_ftw18_0 [7:0] hopf_ftw18[7:0] 0x00 r/w 0x84b hopf_ftw18_1 [7:0] hopf_ftw18[15:8] 0x00 r/w 0x84c hopf_ftw18_2 [7:0] hopf_ftw18[23:16] 0x00 r/w 0x84d hopf_ftw18_3 [7:0] hopf_ftw18[31:24] 0x00 r/w 0x84e hopf_ftw19_0 [7:0] hopf_ftw19[7:0] 0x00 r/w 0x84f hopf_ftw19_1 [7:0] hopf_ftw19[15:8] 0x00 r/w 0x850 hopf_ftw19_2 [7:0] hopf_ftw19[23:16] 0x00 r/w 0x851 hopf_ftw19_3 [7:0] hopf_ftw19[31:24] 0x00 r/w 0x852 hopf_ftw20_0 [7:0] hopf_ftw20[7:0] 0x00 r/w 0x853 hopf_ftw20_1 [7:0] hopf_ftw20[15:8] 0x00 r/w 0x854 hopf_ftw20_2 [7:0] hopf_ftw20[23:16] 0x00 r/w 0x855 hopf_ftw20_3 [7:0] hopf_ftw20[31:24] 0x00 r/w 0x856 hopf_ftw21_0 [7:0] hopf_ftw21[7:0] 0x00 r/w 0x857 hopf_ftw21_1 [7:0] hopf_ftw21[15:8] 0x00 r/w 0x858 hopf_ftw21_2 [7:0] hopf_ftw21[23:16] 0x00 r/w 0x859 hopf_ftw21_3 [7:0] hopf_ftw21[31:24] 0x00 r/w 0x85a hopf_ftw22_0 [7:0] hopf_ftw22[7:0] 0x00 r/w 0x85b hopf_ftw22_1 [7:0] hopf_ftw22[15:8] 0x00 r/w 0x85c hopf_ftw22_2 [7:0] hopf_ftw22[23:16] 0x00 r/w 0x85d hopf_ftw22_3 [7:0] hopf_ftw22[31:24] 0x00 r/w 0x85e hopf_ftw23_0 [7:0] hopf_ftw23[7:0] 0x00 r/w 0x85f hopf_ftw23_1 [7:0] hopf_ftw23[15:8] 0x00 r/w 0x860 hopf_ftw23_2 [7:0] hopf_ftw23[2 3:16] 0x00 r/w 0x861 hopf_ftw23_3 [7:0] hopf_ftw23[31:24] 0x00 r/w 0x862 hopf_ftw24_0 [7:0] hopf_ftw24[7:0] 0x00 r/w 0x863 hopf_ftw24_1 [7:0] hopf_ftw24[15:8] 0x00 r/w 0x864 hopf_ftw24_2 [7:0] hopf_ftw24[23:16] 0x00 r/w 0x865 hopf_ftw24_3 [7:0] hopf_f tw24[31:24] 0x00 r/w 0x866 hopf_ftw25_0 [7:0] hopf_ftw25[7:0] 0x00 r/w 0x867 hopf_ftw25_1 [7:0] hopf_ftw25[15:8] 0x00 r/w 0x868 hopf_ftw25_2 [7:0] hopf_ftw25[23:16] 0x00 r/w 0x869 hopf_ftw25_3 [7:0] hopf_ftw25[31:24] 0x00 r/w
data sheet AD9164 rev. a | page 81 of 136 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x86a hopf_ftw26_0 [7:0] hopf_ftw26[7:0] 0x00 r/w 0x86b hopf_ftw26_1 [7:0] hopf_ftw26[15:8] 0x00 r/w 0x86c hopf_ftw26_2 [7:0] hopf_ftw26[23:16] 0x00 r/w 0x86d hopf_ftw26_3 [7:0] hopf_ftw26[31:24] 0x00 r/w 0x86e hopf_ftw27_0 [7:0] hopf_ftw27[7:0] 0x00 r/w 0x86f hopf_ftw27_1 [7 :0] hopf_ftw27[15:8] 0x00 r/w 0x870 hopf_ftw27_2 [7:0] hopf_ftw27[23:16] 0x00 r/w 0x871 hopf_ftw27_3 [7:0] hopf_ftw27[31:24] 0x00 r/w 0x872 hopf_ftw28_0 [7:0] hopf_ftw28[7:0] 0x00 r/w 0x873 hopf_ftw28_1 [7:0] hopf_ftw28[15:8] 0x00 r/w 0x874 hopf_ftw28 _2 [7:0] hopf_ftw28[23:16] 0x00 r/w 0x875 hopf_ftw28_3 [7:0] hopf_ftw28[31:24] 0x00 r/w 0x876 hopf_ftw29_0 [7:0] hopf_ftw29[7:0] 0x00 r/w 0x877 hopf_ftw29_1 [7:0] hopf_ftw29[15:8] 0x00 r/w 0x878 hopf_ftw29_2 [7:0] hopf_ftw29[23:16] 0x00 r/w 0x879 hopf _ftw29_3 [7:0] hopf_ftw29[31:24] 0x00 r/w 0x87a hopf_ftw30_0 [7:0] hopf_ftw30[7:0] 0x00 r/w 0x87b hopf_ftw30_1 [7:0] hopf_ftw30[15:8] 0x00 r/w 0x87c hopf_ftw30_2 [7:0] hopf_ftw30[23:16] 0x00 r/w 0x87d hopf_ftw30_3 [7:0] hopf_ftw30[31:24] 0x00 r/w 0x87 e hopf_ftw31_0 [7:0] hopf_ftw31[7:0] 0x00 r/w 0x87f hopf_ftw31_1 [7:0] hopf_ftw31[15:8] 0x00 r/w 0x880 hopf_ftw31_2 [7:0] hopf_ftw31[23:16] 0x00 r/w 0x881 hopf_ftw31_3 [7:0] hopf_ftw31[31:24] 0x00 r/w
AD9164 data sheet rev. a | page 82 of 136 register details table 46 . register details hex . addr . name bits bit name settings description reset access 0x000 spi_intfconfa 7 softreset_m soft reset (mirror) . set this to mirror bit 0 . 0x0 r 6 lsbfirst_m lsb first (mirror ) . set this to mirror bit 1 . 0x0 r 5 addrinc_m addr ess increment (mirror). set this to mirror bit 2 . 0x0 r 4 sdoactive_m sdo active (mirror). set this to mirror bit 3 . 0x0 r 3 sdoactive sdo a ctive. enables 4 - wire spi bus mode. 0x0 r/w 2 addrinc addr ess i nc rement . when set , causes incremen ting streaming addresses ; otherwise , descending addresses are generated. 0x0 r/w 1 streaming a ddresses are i ncremented. 0 streaming a ddresses are d ecr e mented. 1 lsbfirst lsb f irst. when set , causes input and output data to be oriented as lsb first. if this bit is clear, data is oriented as msb first. 0x0 r/w 1 shift lsb in first. 0 shift msb in f irst. 0 softreset soft r eset. this bit automatically clears to 0 after performing a reset operation. setting this bit init iates a reset. this bit is auto clearing after the soft reset is complete. 0x0 r/w 1 pulse the soft reset li ne. 0 reset the soft rese t line. 0x001 spi_intfconfb 7 singleins single i nst r uction . 0x0 r/w 1 perform single transf ers. 0 perf orm multiple tran sfers. 6 cs stall cs s talling . 0x0 r/w 0 disable cs s talling. 1 enable cs s talling. [5:3] reserved reserved. 0x0 r/w 2 softreset1 soft reset 1. this bit automatically clears to 0 after performing a reset operation. 0x0 r/w 1 pulse the soft reset 1 line. 0 pulse the soft reset 1 line. 1 softreset0 soft reset 0. this bit automatically clears to 0 after performing a reset opera tion. 0x0 r/w 1 pulse the soft reset 0 line. 0 pulse the soft reset 0 line. 0 reserved reserved. 0x0 r
data sheet AD9164 rev. a | page 83 of 136 hex . addr . name bits bit name settings description reset access 0x002 spi_devconf [7:4] devstatus device s tatus . 0x0 r/w [3:2] custopmode customer o perating m ode . 0x0 r/w [1:0] sysopmode sy stem o perating m ode . 0x0 r/w 0 normal o peration. 1 low p ower o peration. 2 medium p ower s tandby. 3 low p ower s leep. 0x003 spi_chiptype [7:0] chip_type chip t ype . 0x0 r 0x004 spi_prodidl [7:0] prod_id[7:0] product id . 0x0 r 0 x005 spi_prodidh [7:0] prod_id[15:8] product id . 0x0 r 0x006 spi_chipgrade [7:4] prod_grade product g rade . 0x0 r [3:0] dev_revision device r evision . 0x0 r 0x020 irq_enable [7:5] reserved reserved. 0x0 r 4 en_sysref_jitter enable sysref jitter interrupt . 0x0 r/w 0 disable interrupt. 1 enable interrupt. 3 en_data_ready enable jesd204x receiver ready (jrx_ data_ready ) low interrupt . 0x0 r/w 0 di s able interrupt. 1 enable interrupt. 2 en_lane_fifo enable l ane fifo overflow/ underflow interrupt . 0x0 r/w 0 disable interrupt. 1 enable interrupt. 1 en_prbsq enable prbs imaginary error interrupt . 0x0 r/w 0 d i s able interrupt. 1 enable interrupt. 0 en_prbsi enable prbs real error interr upt . 0x0 r/w 0 disable interrupt. 1 enable interrupt. 0x024 irq_status [7:5] reserved reserved. 0x0 r 4 irq_sysref_jitter sysref jitter is too big. writing 1 clear s the status . 0x0 r/w 3 irq_data_ready jrx _ data_ready is low. writin g 1 clear s the status . 0x0 r/w 0 no warning. 1 warning detected. 2 irq_lane_fifo lane fifo overflow/underflow . writing 1 clear s the status . 0x0 r/w 0 no warning. 1 warning detected. 1 irq_prbsq prbs imag inary error. writ ing 1 clear s the status . 0x0 r/w 0 no warning. 1 warning detected. 0 irq_prbsi prbs real error. writing 1 clear s the status . 0x0 r/w 0 no warning. 1 warning detected. 0x031 sync_lmfc_delay_frame [7:5] reserved reserved. 0x 0 r [4:0] sync_lmfc_delay_set_frm desired delay from rising edge of sysref input to rising edge of lm f c in frames . 0x0 r/w
AD9164 data sheet rev. a | page 84 of 136 hex . addr . name bits bit name settings description reset access 0x032 sync_lmfc_delay0 [7:0] sync_lmfc_delay_set[7:0] desired delay from rising edge of sysref input to rising edge of lmfc i n dac clock units . 0x0 r/w 0x033 sync_lmfc_delay1 [7:4] reserved reserved. 0x0 r [3:0] sync_lmfc_delay_set[11:8] desired delay from rising edge of sysref input to rising edge of lmfc in dac clock units . 0x0 r/w 0x034 sync_lmfc_stat0 [7:0] sync_lmfc _delay_stat[7:0] measured delay from rising edge of sysref input to rising edge of lmfc in dac clock units (note: 2 lsbs are always zero). a write to sync_lmfc_stat x or sysref_ phase x save s the data for readback. 0x0 r/w 0x035 sync_lmfc_stat1 [7:4] reser ved reserved. 0x0 r [3:0] sync_lmfc_delay_stat[11:8] measured delay from rising edge of sysref input to rising edge of lmfc in dac clock units (note: 2 lsbs are always zero). a write to sync_lmfc_stat x or sysref_ phase x save s the data for readback. 0x 0 r/w 0x036 sysref_count [7:0] sysref_count count of sysref signal s received. a write reset s the count. a write to sync_lmfc_stat x or sysref_ phase x save s the data for readback. 0x0 r/w 0x037 sysref_phase0 [7:0] sysref_phase[7:0] phase of measured sysr ef event. thermometer encoded. a write to sync_lmfc_stat x or sysref_phase x save s the data for readback. 0x0 r/w 0x038 sysref_phase1 [7:4] reserved reserved. 0x0 r [3:0] sysref_phase[11:8] phase of measured sysref event. thermometer encoded. a write to sync_lmfc_stat x or sysref_phase x save s the data for readback. 0x0 r/w 0x039 sysref_jitter_window [7:6] reserved reserved. 0x0 r [5:0] sysref_jitter_window amount of jitter allowed on the sysref input. sysref jitter variations bigger than this t rigger s an interrupt. units are in dac clocks. the bottom two bits are ignored. 0x0 r/w 0x03a sync_ctrl [7:2] reserved reserved. 0x0 r [1:0] sync_mode synchronization mode . 0x0 r/w 00 do not perform synchronization, monitor sysref to lmfc delay only. 01 perform continuous synchroniza - tion of lmfc on every sysref . 10 perform a single synchronization on the next sysref , then switch to monitor mode.
data sheet AD9164 rev. a | page 85 of 136 hex . addr . name bits bit name settings description reset access 0x03f tx_enable 7 spi_datapath_post spi control of the data at the output of the datapath . 0x1 r/w 0 disable or zero the data from the datapath into the dac. 1 use the data from the datapath to drive the dac. 6 spi_datapath_pre spi control of the data at the input of the datapath . 0x1 r/w 0 disable or zero the d ata feeding into the datapath. 1 use the data from the jesd 204b lanes to drive into the datapath. [5:4] reserved reserved. 0x0 r 3 txen_nco_reset allows tx_enable to control the dds nco reset . 0x0 r/w 0 use the spi ( hopf_mode bits to control the dds nco reset . 1 use the tx_enable pin to control the dds nco reset. 2 txen_datapath_post allows tx_enable to control the data at the output of the datapath . 0x0 r/w 0 use the spi ( bit spi_datapath_ post ) for control. 1 use the tx_enable pin for control. 1 txen_datapath_pre allows tx_enable to control the data at the input of the datapath . 0x0 r/w 0 use the spi ( bit spi_datapath_ pre ) for control. 1 use the tx_enable pin for control. 0 txen_dac_fsc allows tx_enable to control the dac full - scale current . 0x0 r/w 0 use the spi register ana_fsc0 and ana_fsc1 for control. 1 use the tx_enable pin for control. 0x040 ana_dac_bias_pd [7:2] reserved reserved. 0x0 r 1 ana_dac_bias_pd1 pow ers down the dac core bias circuits. a 1 powers down the dac core bias circuits. 0x1 r/w 0 ana_dac_bias_pd0 powers down the dac core bias circuits. a 1 powers down the dac core bias circuits. 0x1 r/w 0x041 ana_fsc0 [7:2] reserved reserved. 0x0 r [ 1:0] ana_full_scale_current[1:0] dac full - scale current. analog full - scale current adjust ment . 0x3 r/w 0x042 ana_fsc1 [7:0] ana_full_scale_current[9:2] dac full - scale current. analog full - scale current adjust ment . 0xff r/w
AD9164 data sheet rev. a | page 86 of 136 hex . addr . name bits bit name settings description reset access 0x07f clk_phase_tune [7:6] re served reserved. 0x0 r [5:0] clk_phase_tune fine tuning of the clock input phase balance. adds small capacitors to the clk + /clk inputs, 20 ff per step, signed magnitude. 0x0 r/w bits[5:0] capacitance at clk+ at clk? 000000 0 0 000001 1 0 000010 2 0 011111 31 0 100000 0 0 100001 0 1 100010 0 2 111111 0 31 0x080 clk_pd [7:1] reserved reserved. 0x0 r 0 dacclk_pd dac clock power - down . powers down the da c clock circuitry. 0x1 r/w 0 power up . 1 power down . 0x082 clk_duty 7 clk_duty_en enable duty cycle control . 0x1 r/w 6 clk_duty_offset_en enable duty cycle offset . 0x0 r/w 5 clk_duty_boost_en enable duty cycle range boost . extends range to 5 at cost of 1 db to 2 db worse phase noise. 0x0 r/w [4:0] clk_duty_prg program the duty cycle offset. 5 - bit signed magnitude field, with the msb as the sign bit and the four lsbs as the magnitude from 0 to 15. a larger magnitude skew s duty cycle to a greater amount. range is 3. 0x0 r/w 0x083 clk_crs_ctrl 7 clk_crs_en enable clock cross control adjustment . 0x1 r/w [6:4] reserved reserved. 0x0 r [3:0] clk_crs_adj program the clock crossing point . 0x0 r/w 0x084 pll_ref_clk_pd [7:6 ] reserved reserved. 0x0 r [5:4] pll_ref_clk_rate pll reference clock rate multiplier . 0x0 r/w 00 normal rate (1 ) pll reference clock. 01 double rate (2 ) pll reference clock. 10 quadruple rate (4 ) pll reference clock. 11 d isable the pll reference clock. [3:1] reserved reserved. 0x0 r 0 pll_ref_clk_pd pll reference clock power - down . 0x0 r/w 0 enable the pll reference clock. 1 power down the pll reference clock.
data sheet AD9164 rev. a | page 87 of 136 hex . addr . name bits bit name settings description reset access 0x088 sysref_ctrl0 [7:4] reserved rese rved. 0x0 r 3 hys_on sysref h ysteresis enable. this bit enables the programmable hysteresis control for the sysref receiver. 0x0 r/w 2 sysref_rise use sysref rising edge. 0x0 r/w [1:0] hys_cntrl[9:8] controls the amount of hysteresis in the sysref receiver. each of the 10 bits adds 10 mv of differential hysteresis to the receiver input. 0x0 r/w 0x089 sysref_ctrl1 [7:0] hys_cntrl[7:0] controls the amount of hysteresis in the sysref receiver. each of the 10 bits adds 10 mv of differential h ysteresis to the receiver input. 0x0 r/w 0x090 dll_pd [7:5] reserved reserved. 0x0 r 4 dll_fine_dc_en fine delay line duty cycle correction enable . 0x1 r/w 3 dll_fine_xc_en fine delay line cross control enable . 0x1 r/w 2 dll_coarse_dc_en coar se delay line duty cycle correction enable . 0x1 r/w 1 dll_coarse_xc_en coarse delay line cross control enable . 0x1 r/w 0 dll_clk_pd power s down dll and digital clock generator . 0x1 r/w 0 power up dll controller. 1 power down dll control ler. 0x091 dll_ctrl 7 dll_track_err track error behavior . 0x1 r/w 0 continue on error. 1 restart on error. 6 dll_search_err search error behavior . 0x1 r/w 0 stop on error. 1 retry on error. 5 dll_slope desired slope . 0x1 r/w 0 negative slope. 1 positive slope. [4:3] dll_search search direction . 0x2 r/w 00 search down from initial point only. 01 search up from initial point only. 10 search up and down from initial point. [2:1] dll_mode controller mode . 0x0 r/w 00 search then track. 01 track only. 10 search only. 0 dll_enable controller enable . 0x0 r/w 0 disable dll controller : u se static spi settings. 1 enable dll controller : u se controller with feedback loop. 0x092 dll_status [7:3] reserved reserved. 0x0 r 2 dll_fail the dac clock dll failed to lock. 0x0 r 1 dll_lost the dac clock dll has lost lock. 0x0 r/w 0 dll_locked the dac clock dll has achieved lock. 0x0 r
AD9164 data sheet rev. a | page 88 of 136 hex . addr . name bits bit name settings description reset access 0x093 dll_gb [7:4] reserved reserved. 0x0 r [3:0] dll_guard search guard band . 0x0 r/w 0x094 dll_coarse [7:6] reserved reserved. 0x0 r [5:0] dll_coarse coarse delay line setpoint . 0x0 r/w 0x095 dll_fine [7:0] dll_fine fine delay line setpoint . 0x80 r/w 0 x096 dll_phase [7:5] reserved reserved. 0x0 r [4:0] dll_phs desired phase . 0x8 r/w 0 minimum allowed phase. 16 maximum allowed phase. 0x097 dll_bw [7:5] reserved reserved. 0x0 r [4:2] dll_filt_bw phase measurement filter bandwidth . 0x0 r/w [1:0] dll_weight tracking speed . 0x0 r/w 0x098 dll_read [7:1] reserved reserved. 0x0 r 0 dll_read read request: 0 to 1 transition update s the coarse, fine, and phase readback values . 0x0 r/w 0x099 dll_coarse_rb [7:6] reserved reserved. 0x0 r [5:0] dll_coarse_rb coarse delay line readback . 0x0 r 0x09a dll_fine_rb [7:0] dll_fine_rb fine delay line readback . 0x0 r 0x09b dll_phase_rb [7:5] reserved reserved. 0x0 r [4:0] dll_phs_rb phase readback . 0x0 r 0x09d dig_clk_invert [7:3 ] reserved reserved. 0x0 r 2 inv_dig_clk invert d igital c lock from dll . 0x0 r/w 0 normal p olarity. 1 inverted p olarity. 1 dig_clk_dc_en digital clock duty cycle correction enable . 0x1 r/w 0 dig_clk_xc_en digital clock cross contr ol enable . 0x1 r/w 0x0a0 dll_clk_debug 7 dll_test_en dll clock output test enable . 0x0 r/w [6:2] reserved reserved. 0x0 r [1:0] dll_test_div dll clock output divide . 0x0 r/w 0x110 interp_mode [7:4] jesd_lanes number of jesd 204b lanes. for prope r operation of the jesd 204b data link, this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x8 r/w [3:0] interp_mode interpolation m ode. for proper operation of the jesd 204b data link, this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1 r/w 0000 1 (bypass) . 0001 2 . 0010 3 . 0011 4 . 0100 6 . 0101 8 . 0110 12 . 0111 16 . 1000 24 .
data sheet AD9164 rev. a | page 89 of 136 hex . addr . name bits bit name settings description reset access 0x111 datapath_cfg 7 invsinc_en inverse sinc filter enable . 0x0 r/w 0 disable inverse sinc filter. 1 enable inverse sinc filter. 6 nco_en modulation enable . 0x0 r/w 0 disable nco. 1 enable nco. 5 reserved reserved. 0x0 r 4 filt_bw datapath f ilter b andwidth . 0x0 r/w 0 filter bandwidth is 80 . 1 filter bandwidth is 90 . 3 reserved reserved. 0x0 r 2 modulus_en modulus dds enable . 0x0 r/w 0 disable modulus dds. 1 enable modulus dds. 1 sel_sideband selects upper or lower sideband from modulation result . 0x0 r/w 0 use upper sideband. 1 use lower sideband spectral flip. 0 fir85_filt_en fir85 filter enable . 0x0 r/w 0x113 ftw_update 7 reserved reserved. 0x0 r [6:4] ftw_req_mode frequency tuning word automatic update mode . 0x0 r/w 000 no automatic requests are generated when the ftw registers are written. 001 automaticall y generate ftw_load_req after ftw0 is written. 010 automatically generate ftw_load_req after ftw1 is written. 011 automatically generate ftw_load_req after ftw2 is written. 100 automatically generate ftw_load_req after ftw3 is written. 101 automatically generate ftw_load_req after ftw4 is written. 110 automatically generate ftw_load_req after ftw5 is written. 3 reserved reserved. 0x0 r 2 ftw_load_sysref ftw load and reset from rising edge of sysref . 0x0 r/w 1 ftw_load_ack frequency tuning word update acknowledge . 0x0 r 0 ftw is not loaded. 1 ftw is loaded. 0 ftw_load_req frequency tuning word update request from spi . 0x0 r/w 0 clear ftw_load_ack. 1 0 to 1 transition load s the ftw . 0x114 ftw0 [7:0] ftw[7:0] nco frequency tuning word. this is x in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ) . 0x0 r/w
AD9164 data sheet rev. a | page 90 of 136 hex . addr . name bits bit name settings description reset access 0x115 ftw1 [7:0] ftw[15:8] nco frequency tuning word. this is x in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). 0x0 r/w 0x116 ftw2 [7:0] ftw[23:16] nco frequency tuning word. this is x in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). 0x0 r/w 0x117 ftw3 [7:0] ftw[31:24] nco frequency tuning word. this is x in the equation f out f dac (m/ n) f dac ((x + a/b)/2 48 ). 0x0 r/w 0x118 ftw4 [7:0] ftw[39:32] nco frequency tuning word. this is x in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). 0x0 r/w 0x119 ftw5 [7:0] ftw[47:40] nco frequency tuning word. this is x in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). 0x0 r/w 0x11c phase_offset0 [7:0] nco_phase_offset[7:0] nco phase offset . 0x0 r/w 0x11d phase_offset1 [7:0] nco_phase_offset[15:8] nco phase offset . 0x0 r/w 0x124 acc_modulus0 [7:0] acc_modulus[7:0] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this m odulus value is used for all nco ftws. 0x0 r/w 0x125 acc_modulus1 [7:0] acc_modulus[15:8] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. 0x0 r/w 0x126 acc_modulus2 [7:0] acc_modulus[23:16] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ).note this modulus value is used for all nco ftws. 0x0 r /w 0x127 acc_modulus3 [7:0] acc_modulus[31:24] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. 0x0 r/w 0x128 acc_modulus4 [7:0] acc_modulus[39:32] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. 0x0 r/w 0x129 acc_modulus5 [7:0] acc_modulus[47:40] dds modulus. this is b in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. 0x0 r/w 0x12a acc_delta0 [7:0] acc_delta[7:0] dds delta. this is a in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. note this delta value is used for all nco ftws. 0x0 r/w 0x12b acc_delta1 [7:0] acc_delta[15:8] dds delta. this is a in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. note this delta value is used for all nco ftws. 0x0 r/w 0x12c acc_delta2 [7:0] acc_delta[23:16] dds delta. this is a in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. note this delta value is used for all nco ftws. 0x0 r/w
data sheet AD9164 rev. a | page 91 of 136 hex . addr . name bits bit name settings description reset access 0x12d acc_delta3 [7 :0] acc_delta[31:24] dds delta. this is a in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ) . note this d elta value is used for all nco ftws. 0x0 r/w 0x12e acc_delta4 [7:0] acc_delta[39:32] dds delta. this is a in the equation f out f dac (m /n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. note this delta value is used for all nco ftws. 0x0 r/w 0x12f acc_delta5 [7:0] acc_delta[47:40] dds delta. this is a in the equation f out f dac (m/n) f dac ((x + a/b)/2 48 ). note this modulus value is used for all nco ftws. note this delta value is used for all nco ftws. 0x0 r/w 0x132 temp_sens_lsb [7:0] temp_sens_out[7:0] output of the temperature sensor adc. 0x0 r 0x133 temp_sens_msb [7:0] temp_sens_out[15:8] output of the temperature sensor adc. 0x0 r 0x134 temp_sens_update [7:1] reserved reserved. 0x0 r 0 temp_sens_update set to 1 to update the temperature sensor reading with a new value. 0x0 r/w 0x135 temp_sens_ctrl 7 temp_sens_fast a 1 sets the temperatur e sensor digital filter bandwidth wider for faster settling time. 0x0 r/w [6:1] reserved reserved. 0x10 r/w 0 temp_sens_enable set to 1 to enable the t emperature sensor. 0x0 r/w 0x14b prbs 7 prbs_good_q good data indicator imag inary channel . 0x 0 r 0 incorrect sequence detected. 1 correct prbs sequence detected. 6 prbs_good_i good data indicator real channel . 0x0 r 0 incorrect sequence detected. 1 correct prbs sequence detected. 5 reserved reserved. 0x0 r 4 prbs_inv_q data i nversion imaginary channel . 0x1 r/w 0 expect normal data. 1 expect inverted data. 3 prbs_inv_i data i nversion real channel . 0x0 r/w 0 expect normal data. 1 expect inverted data. 2 prbs_mode polynomial s elect . 0x0 r/w 0 7 - bit: x 7 + x 6 + 1. 1 15 - bit: x 15 + x 14 + 1. 1 prbs_reset reset e rror c ounters . 0x0 r/w 0 normal operation. 1 reset counters. 0 prbs_en enable prbs c hecker . 0x0 r/w 0 disable . 1 enable . 0x 14c prbs_error_i [7:0] prbs_count_i error count value real channel . 0x0 r 0x14d prbs_error_q [7:0] prbs_count_q error c ount v alue i mag inary c hannel . 0x0 r 0x14e test_dc_data1 [7:0] dc_test_data[15:8] dc test data. 0x0 r/w
AD9164 data sheet rev. a | page 92 of 136 hex . addr . name bits bit name settings description reset access 0x14f test_dc_data0 [7:0] d c_test_data[7:0] dc test data. 0x0 r/w 0x150 dig_test [7:2] reserved reserved. 0x0 r 1 dc_test_en dc data test mode enable. 0x0 r/w 1 dc test mode enable. 0 dc test mode disable. 0 reserved reserved. 0x0 r/w 0x151 decode_ctrl [7 :3] reserved reserved. 0x0 r/w 2 shuffle shuffle m ode. enables shuffle mode for better spurious performance . 0x0 r/w 0 disable msb shuffling (use thermometer encoding) . 1 enable msb shuffling. [1:0] reserved reserved. 0x0 r/w 0x152 decode_mode [7:2] reserved reserved. 0x0 r [1:0] decode_mode decode mode . 0x0 r/w 00 non return - to - zero mode (first nyquist ) . 01 mix - mode (second nyquist ) . 10 return to z ero. 11 reserved. 0x1df spi_strength [7:4] reserved reserved. 0x0 r [3:0] spidrv slew and drive strength for cmos spi outputs. s lew bits [1:0] , drive bits [3:2] . 0xf r/w 0x200 master_pd [7:1] reserved reserved. 0x0 r 0 spi_pd_master power s down the entire jesd 204b rx analog (all eight channels a nd bias). 0x1 r/w 0x201 phy_pd [7:0] spi_pd_phy spi override to power down the individual phys. 0x0 r/w bit 0 controls the serdin0 phy. bit 1 controls the serdin1 phy. bit 2 controls the serdin2 phy. bit 3 controls the s erdin3 phy. bit 4 controls the serdin4 phy. bit 5 controls the serdin5 phy. bit 6 controls the serdin6 phy. bit 7 controls the serdin7 phy. 0x203 generic_pd [7:2] reserved reserved. 0x0 r 1 spi_sync1_pd power s d own lvds buffer for the sync request signal , syncout . 0x0 r/w 0 reserved reserved. 0x0 r/w 0x206 cdr_reset [7:1] reserved reserved. 0x0 r 0 spi_cdr_ reset resets the digital control logic for all phys. 0x1 r/ w 0 cdr logic is reset. 1 cdr logic is operational. 0x230 cdr_operating_mode_reg_0 [7:6] reserved reserved. 0x0 r/w 5 spi_enhalfrate enables half rate cdr operation, must be enabled for data rates above 6 gbps. 0x1 r/w 0 disables c dr half rate operation, data rate 6 gbps. 1 enables cdr half rate operation, data rate 6 gbps.
data sheet AD9164 rev. a | page 93 of 136 hex . addr . name bits bit name settings description reset access [4:3] reserved reserved. 0x 1 r/w [2:1] spi_division_rate enables oversampling of the input data. 0x0 r/w 00 no division. data rate 3 gbps. 01 division by 2. 1.5 gbps d ata rate 3 gbps. 10 division by 4. 750 mbps d ata rate 1.5 gbps. 0 reserved reserved. 0x0 r/w 0x250 eq_config_phy_0_1 [7:4] spi_eq_config1 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1 . 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost leve l 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. [3:0] spi_eq_config0 0x8 r/w 0000 manual mode ( spi configured values used) . 000 1 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. 0x251 eq_config_phy_2_3 [7:4] spi_eq_config3 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6.
AD9164 data sheet rev. a | page 94 of 136 hex . addr . name bits bit name settings description reset access 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. [3:0] spi_eq_config2 0x8 r/w 0 000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. 0x252 eq_config_phy_4_ 5 [7:4] spi_eq_config5 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boos t level 15. [3:0] spi_eq_config4 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 01 10 boost level 6.
data sheet AD9164 rev. a | page 95 of 136 hex . addr . name bits bit name settings description reset access 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. 0x253 eq_config_phy_6_7 [7:4] spi_eq_config7 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost le vel 13. 1110 boost level 14. 1111 boost level 15. [3:0] spi_eq_config6 0x8 r/w 0000 manual mode ( spi configured values used) . 0001 boost level 1. 0010 boost level 2. 0011 boost level 3. 0100 boost level 4. 0101 boost level 5. 0110 boost level 6. 0111 boost level 7. 1000 boost level 8. 1001 boost level 9. 1010 boost level 10. 1011 boost level 11. 1100 boost level 12. 1101 boost level 13. 1110 boost level 14. 1111 boost level 15. 0x268 eq_bias_reg [7:6] eq_power_mode controls the equalizer power mode/insertion loss capability . 0x1 r/w 00 normal mode. 01 low power mode. [5:0] reserved reserved. 0x4 r/w
AD9164 data sheet rev. a | page 96 of 136 hex . addr . name bits bit name settings description reset access 0x280 synth_enable_cntrl [7:3] reserved reserved. 0x0 r 2 spi_recal_synth set this bit h igh to rerun all of the serdes pll calibration routines. s et this bit low again to allow additional recalibrations. rising edge causes the calibration. 0x0 r/w 1 reserved reserved. 0x0 r/w 0 spi_enable_synth enable the serdes pll. setting this bit turns on all currents and proceeds to calibrate the pll. make sure reference clock and division ratios are correct before enabling thi s bit. 0x0 r/w 0x281 pll_status [7:6 ] reserved reserved. 0x0 r 5 spi_cp_over_range_high_rb if set, the serdes pll cp output is above valid operating range. 0x0 r 0 charge pump output is within operating range. 1 charge pump output is abo ve operating range. 4 spi_cp_over_range_low_rb if set, the serdes pll cp output is below valid operating range. 0x0 r 0 charge pump output is within operating range. 1 charge pump output is below operating range. 3 spi_cp_cal_valid_r b this bit tells the user if the charge pump cal ibration has completed and is valid . 0x0 r 0 charge pump calibration is not valid. 1 charge pump calibration is valid. [2:1] reserved reserved. 0x0 r 0 spi_pll_lock_rb if set, the serd es synth esizer locked . 0x0 r 0 pll is not locked. 1 pll is locked. 0x289 ref_clk_divider_ldo [7:2] reserved reserved. 0x0 r [1:0] serdes_pll_div_factor serdes pll r eference c lock d ivision f actor. this field controls the division of the serdes pll reference clock before it is fed into the serdes pll pfd. it must be set so that f ref /divfactor is between 35 mhz and 80 mhz. 0x0 r/w 00 divide by 4 for lane rate between 6 gbps and 12.5 gbps. 01 divide by 2 for lane rate between 3 gbps and 6 gbps. 10 divide by 1 for lane rate between 1.5 gbps and 3 gbps. 0x2a7 term_blk1_ctrlreg0 [7:1] reserved reserved. 0x0 r 0 spi_i_tune_r_cal_termblk1 rising edge of this bit starts a termination calibration routine. 0x0 r/w
data sheet AD9164 rev. a | page 97 of 136 hex . addr . name bits bit name settings description reset access 0x2a8 t erm_blk1_ctrlreg1 [7:0] spi_i_serializer_rtrim_termblk1 spi override for termination value for phy 0, phy 1, phy 6, and phy 7. value options are as follows : 0x0 r/w xxx0xxxx automatically calibrate termination value. xxx1000x force 000 as term ination value. xxx1001x force 001 as termination value. xxx1010x force 010 as termination value. xxx1011x force 011 as termination value. xxx1100x force 100 as termination value. xxx1101x force 101 as termination value. xxx1110x force 110 as termination value. xxx1111x force 111 as termination value. xxx1000x force 000 as termination value. 0x2ac term_blk1_rd_reg0 [7:4] reserved reserved. 0x0 r [3:0] spi_o_rcal_code_termblk1 readback of calibra tion code for phy 0, phy 1, phy 6, and phy 7. 0x0 r 0x2ae term_blk2_ctrlreg0 [7:1] reserved reserved. 0x0 r 0 spi_i_tune_r_cal_termblk2 rising edge of this bit starts a termination calibration routine. 0x0 r/w 0x2af term_blk2_ctrlreg1 [7:0] spi_i_se rializer_rtrim_termblk2 spi override for termination value for phy 2, phy 3, phy 4, and phy 5. value options are as follows : 0x0 r/w xxx0xxxx automatically calibrate termination value. xxx1000x force 000 as termination value. xxx1001x f orce 001 as termination value. xxx1010x force 010 as termination value. xxx1011x force 011 as termination value. xxx1100x force 100 as termination value. xxx1101x force 101 as termination value. xxx1110x force 110 as term ination value. xxx1111x force 111 as termination value. xxx1000x force 000 as termination value. 0x2b3 term_blk2_rd_reg0 [7:4] reserved reserved. 0x0 r [3:0] spi_o_rcal_code_termblk2 readback of calibration code for phy 2, phy 3, phy 4, and phy 5. 0x0 r 0x2bb term_offset_0 [7:4] reserved reserved. 0x0 r [3:0] term_offset_0 add or subtract from the termination calibration value of physical lane 0. 4 - bit signed magnitude value that adds to or subtracts from the termination value. b it 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2bc term_offset_1 [7:4] reserved reserved. 0x0 r [3:0] term_offset_1 add or subtract from the termination calibration value of physical lane 1. 4 - bit signed magnitude value that ad ds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w
AD9164 data sheet rev. a | page 98 of 136 hex . addr . name bits bit name settings description reset access 0x2bd term_offset_2 [7:4] reserved reserved. 0x0 r [3:0] term_offset_2 add or subtract from the termination calibration value of physi cal lane 2. 4 - bit signed magnitude value that adds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2be term_offset_3 [7:4] reserved reserved. 0x0 r [3:0] term_offset_3 add or subtract from the termination calibration value of physical lane 3. 4 - bit signed magnitude value that adds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2bf term_offset_4 [7:4] reserved reserve d. 0x0 r [3:0] term_offset_4 add or subtract from the termination calibration value of physical lane 4. 4 - bit signed magnitude value that adds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2c0 term_offset_5 [7:4] reserved reserved. 0x0 r [3:0] term_offset_5 add or subtract from the termination calibration value of physical lane 5. 4 - bit signed magnitude value that adds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2c1 term_offset_6 [7:4] reserved reserved. 0x0 r [3:0] term_offset_6 add or subtract from the termination calibration value of physical lane 6. 4 - bit signed magnitude value that adds to or subtrac ts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x2c2 term_offset_7 [7:4] reserved reserved. 0x0 r [3:0] term_offset_7 add or subtract from the termination calibration value of physical lane 7. 4 - bi t signed magnitude value that adds to or subtracts from the termination value. bit 3 is the sign bit, and bits[2:0] are the magnitude bits. 0x0 r/w 0x300 general_jrx_ctrl_0 7 reserved reserved. 0x0 r 6 checksum_mode jesd 204b link parameter checksum c alculation method. 0x0 r/w 0 checksum is sum of fields. 1 checksum is sum of octets. [5:1] reserved reserved. 0x0 r 0 link_en this bit bring s up the jesd 204b receiver when all link parameters are programmed and all clocks are ready . 0x0 r/w 0x302 dyn_link_latency_0 [7:5] reserved reserved. 0x0 r [4:0] dyn_link_latency_0 measurement of the jesd 204b link delay (in pclk units) . link 0 dynamic link l atency . latency between current deframer lmfc and the global lmfc . 0x0 r
data sheet AD9164 rev. a | page 99 of 136 hex . addr . name bits bit name settings description reset access 0x304 lmfc _delay_0 [7:5] reserved reserved. 0x0 r [4:0] lmfc_delay_0 fixed part of the jesd 204b link delay (in pclk units) . delay in f rame clock cycles for global lmfc for link 0 . 0x0 r/w 0x306 lmfc_var_0 [7:5] reserved reserved. 0x0 r [4:0] lmfc_var_0 va riable part of the jesd 204b link delay (in pclk units) . location in r x lmfc where jesd 204b words are read out from buffer . this setting must not be more than 10 pclk s. 0x1f r/w 0x308 xbar_ln_0_1 [7:6] reserved reserved. 0x0 r [5:3] src_lane1 select d ata from serdin0 , serdin1 , , or serdin7 for logic lane 1 . 0x1 r/w 000 data is from serdin0 . 001 data is from serdin1 . 010 data is from serdin2 . 011 data is from serdin3 . 100 data is from serdin4 . 101 data is from serdin5 . 110 data is from serdin6 . 111 data is from serdin7 . [2:0] src_lane0 select data from serdin0, serdin1, , or serdin7 for logic lane 0 . 0x0 r/w 000 data is from serdin0. 001 data is from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7. 0x309 xbar_ln_2_3 [7:6] reserved reserved. 0x0 r [5 :3] src_lane3 select data from serdin0, serdin1, , or serdin7 for logic lane 3 . 0x3 r/w 000 data is from serdin0. 001 data is from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdi n4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7.
AD9164 data sheet rev. a | page 100 of 136 hex . addr . name bits bit name settings description reset access [2:0] src_lane2 select data from serdin0, serdin1, , or serdin7 for logic lane 2 . 0x2 r/w 000 data is from serdin0. 001 data i s from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7. 0x30a xbar_ln_4_5 [7:6] reserved reserved. 0x0 r [5:3] src_lane5 select data from serdin0, serdin1, , or serdin7 for logic lane 5 . 0x5 r/w 000 data is from serdin0. 001 data is from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7. [2:0] src_lane4 select data from serdin0, serdin1, , or serdin7 for logic lane 4 . 0x4 r/w 000 data is from serd in0. 001 data is from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7. 0x30b xba r_ln_6_7 [7:6] reserved reserved. 0x0 r [5:3] src_lane7 select data from serdin0, serdin1, , or serdin7 for logic lane 7 . 0x7 r/w 000 data is from serdin0. 001 data is from serdin1. 010 data is from serdin2. 011 data i s from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7.
data sheet AD9164 rev. a | page 101 of 136 hex . addr . name bits bit name settings description reset access [2:0] src_lane6 select data from serdin0, serdin1, , or serdin7 for logic lane 6 . 0x6 r/w 000 data is from serdin0. 001 data is from serdin1. 010 data is from serdin2. 011 data is from serdin3. 100 data is from serdin4. 101 data is from serdin5. 110 data is from serdin6. 111 data is from serdin7. 0x30c fifo_status_reg_0 [7:0] lane_fifo_full bit 0 corresponds to fifo full flag for data from serdin0 . 0x0 r bit 1 corresponds to fifo full flag for data from serdin1. bit 2 corresponds to fifo full flag for data from serdin 2. bit 3 corresponds to fifo full flag for data from serdin3. bit 4 corresponds to fifo full flag for data from serdin4. bit 5 corresponds to fifo full flag for data from serdin5. bit 6 corresponds to fifo full flag for data from serdin6. bit 7 corresponds to fifo full flag for data from serdin7. 0x30d fifo_status_reg_1 [7:0] lane_fifo_empty bit 0 corresponds to fifo empty flag for data from serdin0. 0x0 r bit 1 corresponds to fifo empty flag for data from serdin1. bit 2 corresponds to fifo empty flag for data from serdin2. bit 3 corresponds to fifo empty flag for data from serdin3. bit 4 corresponds to fifo empty flag for data from serdin4. bit 5 corresponds to fifo empty flag for data from serdin5. bit 6 corresponds to fifo empty flag for data from serdin6. bit 7 corresponds to fifo empty flag for data from serdin7. 0x311 sync _gen_0 [7: 3 ] reserved reserved. 0x0 r 2 eomf_ma sk_0 mask eomf from qbd_0 . assert syncout based on loss of m ulti f rame s ync . 0x0 r/w 0 do no t assert syncout on loss of multiframe. 1 assert syncout on loss of multiframe. 1 reserved reserved. 0x0 r/w 0 eof_mask_0 mask eof from qbd_0 . assert syncout based on loss of frame sync. 0x0 r/w 0 do n o t assert syncout on l oss of f rame. 1 assert syncout on loss of f rame.
AD9164 data sheet rev. a | page 102 of 136 hex . addr . name bits bit name settings description reset access 0x312 sync _gen_1 [7:4] sync _err_dur duration of sync out signal low for purpose of sync error report. 0 means half pclk cycle. add an additional pclk 4 octets for each increment of the value . 0x0 r/w [3:0] sync _syncreq_dur duration of syncout signal low for purpose of sync request. 0 means 5 frame + 9 octets. add an additional pclk 4 octets for each increment of the value . 0x0 r/w 0x313 sync _ gen_3 [7:0] lmfc_period lmfc period in pclk cycle . this is to report the global lmfc period based on pclk. 0x0 r 0x315 phy_prbs_test_en [7:0] phy_test_en enable phy ber by un gating the clocks . 0x0 r/w 1 phy test enable. 0 phy test disable. 0x316 phy_prbs_test_ctrl 7 reserved reserved. 0x0 r [6:4] phy_src_err_cnt 0x0 r/w 000 report lane 0 error count. 001 report lane 1 error count. 010 report lane 2 error count. 011 report lane 3 error count. 100 repor t lane 4 error count. 101 report lane 5 error count. 110 report lane 6 error count. 111 report lane 7 error count. [3:2] phy_prbs_pat_sel s elect prbs pattern for phy ber test . 0x0 r/w 00 prbs7. 01 prbs15. 10 pr bs31. 11 not used. 1 phy_test_start s tart and stop the phy prbs test . 0x0 r/w 0 test not started. 1 test started. 0 phy_test_reset reset phy prbs test state machine and error counters . 0x0 r/w 0 not reset. 1 reset . 0x317 phy_prbs_test_threshold_lobits [7:0] phy_prbs_threshold_lobits bits[7:0] of the 24 - bit threshold value set the error flag for phy prbs test . 0x0 r/w 0x318 phy_prbs_test_threshold_midbits [7:0] phy_prbs_threshold_midbits bits[15:8] of the 24 - b it threshold value set the error flag for phy prbs test . 0x0 r/w 0x319 phy_prbs_test_threshold_hibits [7:0] phy_prbs_threshold_hibits bits[23:16] of the 24 - bit threshold value set the error flag for phy prbs test . 0x0 r/w 0x31a phy_prbs_test_errcnt_lobi ts [7:0] phy_prbs_err_cnt_lobits bits[7:0] of the 24 - bit reported phy ber t est error count from selected lane . 0x0 r 0x31b phy_prbs_test_errcnt_midbits [7:0] phy_prbs_err_cnt_midbits bits[15:8] of the 24 - bit reported phy ber t est error count from select ed lane . 0x0 r 0x31c phy_prbs_test_errcnt_hibits [7:0] phy_prbs_err_cnt_hibits bits[23:16] of the 24 - bit reported phy ber t est error count from selected lane . 0x0 r
data sheet AD9164 rev. a | page 103 of 136 hex . addr . name bits bit name settings description reset access 0x31d phy_prbs_test_status [7:0] phy_prbs_pass each bit is for the corresponding lane. report phy ber t est pass/fail for each lane . 0xff r 0x31e phy_data_snapshot_ctrl [7:5] reserved reserved. 0x0 r [4:2] phy_grab_lane_sel select which lane to grab data . 0x0 r/w 000 grab data from lane 0. 001 grab data from lane 1. 0 10 grab data from lane 2. 011 grab data from lane 3. 100 grab data from lane 4. 101 grab data from lane 5. 110 grab data from lane 6. 111 grab data from lane 7. 1 phy_grab_mode use error trigger to grab data. 0x0 r /w 0 grab data when phy_grab_data is set. 1 grab data upon bit error. 0 phy_grab_data transition from 0 to 1 causes logic to store current receive data from one lane . 0x0 r/w 0x31f phy_snapshot_data_byte0 [7:0] phy_snapshot_data_byte0 c urrent data received represents phy_ snapshot_data [7:0] . 0x0 r 0x320 phy_snapshot_data_byte1 [7:0] phy_snapshot_data_byte1 current data received represents phy_ snapshot_data [15:8] . 0x0 r 0x321 phy_snapshot_data_byte2 [7:0] phy_snapshot_data_byte2 curr ent data received represents phy_ snapshot_data [23:16] . 0x0 r 0x322 phy_snapshot_data_byte3 [7:0] phy_snapshot_data_byte3 current data received represents phy_ snapshot_data [31:24] . 0x0 r 0x323 phy_snapshot_data_byte4 [7:0] phy_snapshot_data_byte4 curren t data received represents phy_ snapshot_data [39:32] . 0x0 r 0x32c short_tpl_test_0 [7:4] short_tpl_sp_sel short transport layer sample sel ection . select which sample to check from a specific dac . 0x0 r/w 0000 sample 0. 0001 sample 1. 00 10 sample 2. 0011 sample 3. 0100 sample 4. 0101 sample 5. 0110 sample 6. 0111 sample 7. 1000 sample 8. 1001 sample 9. 1010 sample 10. 1011 sample 11. 1100 sample 12. 1101 sample 1 3. 1110 sample 14. 1111 sample 15. [3:2] short_tpl_m_sel short transport layer test dac sel ection . select which dac to check . 0x0 r/w 00 dac 0. 01 dac 1. 10 dac 2. 11 dac 3.
AD9164 data sheet rev. a | page 104 of 136 hex . addr . name bits bit name settings description reset access 1 short_tpl_test_reset short t ransport layer test reset. resets the result of short transport layer test . 0x0 r/w 0 not reset. 1 reset. 0 short_tpl_test_en short transport layer test enable. enable short transport layer test. 0x0 r/w 0 disable . 1 enable . 0x32d short_tpl_test_1 [7:0] short_tpl_ref_sp_lsb short transport layer reference sample lsb. this is the lower eight bits of expected dac sample. it is used to compare with the received dac sample at the output of jesd 204b r x . 0x0 r/w 0x32e short_tpl_ test_2 [7:0] short_tpl_ref_sp_msb short transport layer test reference sample msb. this is the upper eight bits of expected dac sample. it is used to compare with the received sample at jesd 204b r x output. 0x0 r/w 0x32f short_tpl_test_3 [7:1] reserved r eserved. 0x0 r 0 short_tpl_fail short transport layer test fail. this bit show s if the selected dac sample matches the reference sample. if they match , the test pass es otherwise , the test fail s . 0x0 r 0 test pass. 1 test fail. 0x334 jes d_bit_inverse_ctrl [7:0] jesd_bit_inverse each bit of this byte inverses the jesd 204b deserialized data from one specific jesd 204b r x phy. the bit order matches the logical lane order. for example, bit 0 controls lane 0, bit 1 controls lane 1. 0x0 r/w 0x 400 did_reg [7:0] did_rd received ilas configuration on lane 0. did is the device id number . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x401 bid_reg [7:0] bid_rd received ila s configuration on lane 0. bid is the bank id, extension to did. link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x402 lid0_reg 7 reserved reserved. 0x0 r 6 adjdir_rd received ilas c onfiguration on lane 0. adjdir is the direction to adjust the dac lmfc . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 5 phadj_rd received ilas configuration on lane 0. phadj is the p hase adjustment request to dac . link information received on lane 0 as specified in section 8.3 of jesd2 04b. 0x0 r
data sheet AD9164 rev. a | page 105 of 136 hex . addr . name bits bit name settings description reset access [4:0] ll_lid0 received ilas lid configuration on lane 0. lid0 is the l a ne i dentification for lane 0 . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x403 scr_l_reg 7 scr_rd received ilas configuration on lane 0. scr is the tx s crambling s tatus . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 scrambling is disabled. 1 scrambling is enabled. [6:5] reserved reserved. 0x0 r [4:0] l_rd received ilas co nfiguration on lane 0. l is the n umber of lanes per converter device . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 00000 1 lane per converter device. 00001 2 lanes per converter device. 00011 4 lanes per converter device. 00111 8 lanes per converter device. 0x404 f_reg [7:0] f_rd received ilas configuration on lane 0. f is the number of octets per frame . settings of 1, 2, and 4 are valid (value in register is f 1) . link information receiv ed on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 1 octet per frame. 1 2 octets per frame. 11 4 octets per frame. 0x405 k_reg [7:5] reserved reserved. 0x0 r [4:0] k_rd received i las configuration on lane 0. k is the n umber of frames per multiframe . settings of 16 or 32 are valid. on this device, all modes use k 32 ( v alue in register is k 1) . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 01111 16 frames per multiframe. 11111 32 frames per multiframe. 0x406 m_reg [7:0] m_rd received i las configuration on lane 0. m is the number of conve rters per device . link information received on lane 0 as specified in section 8.3 of jesd204b. m is 1 for real interf ace and 2 for complex interface (value in register is m 1) . 0x0 r 0x407 cs_n_reg [7:6] cs_rd received il as configuration on lane 0. cs is the n umber of control bits per sample . link information received on lane 0 as specified in section 8.3 of jesd204b. cs is always 0 on this device. 0x0 r 5 reserved reserved. 0x0 r
AD9164 data sheet rev. a | page 106 of 136 hex . addr . name bits bit name settings description reset access [4:0] n_rd received ilas configuration on lane 0. n is the conver ter resolu - tion . value in register is n 1 ( for example , 16 bits 0b01111) . 0x0 r 0x408 np_reg [7:5] subclassv_rd received ilas configuration on lane 0. subclassv is the device s ub c lass version . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 000 sub class 0 . 001 subclass 1. [4:0] np_rd received ilas configuration on lane 0. n p is the total n umber of bits per sample . link information received on lane 0 as specified in section 8.3 of jesd204b. v alue in register is n p 1, for example, 16 bi ts per sample 0b01111 . 0x0 r 0x409 s_reg [7:5] jesdv_rd received ilas configuration on lane 0. jesdv is the jesd204 x version . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 000 jesd204a. 001 jesd204b. [4:0] s_rd received ilas con figuration on lane 0. s is the n umber of samples per converter per frame cycle . link information received on lane 0 as specified in section 8.3 of jesd204b. value in register is s 1. 0x0 r 0x40a hd_cf_reg 7 hd_rd received il as configuration on lane 0. hd is the high density format . refer to section 5.1.3 of jesd204b standard . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0 low density m ode. 1 high density mode. [6:5] reserved reserved. 0x0 r [4:0] cf_rd received ilas configuration on lane 0. cf is the number of control words per frame clock period per link . link information received on lane 0 as specified in section 8.3 of jesd204b. cf is always 0 on this device. 0x0 r 0x40b res1_reg [7:0] res1_rd received ilas configuration on lane 0. reserved field 1 . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x40c res2_reg [7:0] res2_rd rece ived ilas configuration on lane 0. reserved field 2 . link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x40d checksum0_reg [7:0] ll_fchk0 received checksum during ilas on lane 0. checksum for lane 0 . link information rece ived on lane 0 as specified in section 8.3 of jesd204b. 0x0 r
data sheet AD9164 rev. a | page 107 of 136 hex . addr . name bits bit name settings description reset access 0x40e compsum0_reg [7:0] ll_fcmp0 computed checksum on lane 0. computed checksum for lane 0 . the jesd 204b r x computes the checksum of the l ink information received on lane 0 as specified in se ction 8.3 of jesd204b. the computation method is set by the checksum_mode bit ( register 0x300 , bit 6) and must match the likewise calculated checksum in register 0x40d . 0x0 r 0x412 lid1_reg [7:5] reserved reserved. 0x0 r [4:0] ll_lid1 received ilas l id configuration on lane 1. lane identification for lane 1. link information received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x415 checksum1_reg [7:0] ll_fchk1 received checksum during ilas on lane 1. checksum for lane 1. link informati on received on lane 0 as specified in section 8.3 of jesd204b. 0x0 r 0x416 compsum1_reg [7:0] ll_fcmp1 computed checksum on lane 1. computed checksum for lane 1 (see description for register 0x40e) . 0x0 r 0x41a lid2_reg [7:5] reserved reserved. 0x0 r [4:0] ll_lid2 received ilas lid configuration on lane 2. lane identification for lane 2. 0x0 r 0x41d checksum2_reg [7:0] ll_fchk2 received checksum during ilas on lane 2. checksum for lane 2 . 0x0 r 0x41e compsum2_reg [7:0] ll_fcmp2 computed checksum on lane 2. computed checksum for lane 2 (see description for register 0x40e) . 0x0 r 0x422 lid3_reg [7:5] reserved reserved. 0x0 r [4:0] ll_lid3 received ilas lid configuration on lane 3. lane identification for lane 3. 0x0 r 0x425 checksum3_reg [7: 0] ll_fchk3 received checksum during ilas on lane 3. checksum for lane 3 . 0x0 r 0x426 compsum3_reg [7:0] ll_fcmp3 computed checksum on lane 3. computed checksum for lane 3 (see description for register 0x40e) . 0x0 r 0x42a lid4_reg [7:5] reserved reser ved. 0x0 r [4:0] ll_lid4 received ilas lid configuration on lane 4. lane identification for lane 4. 0x0 r 0x42d checksum4_reg [7:0] ll_fchk4 received checksum during ilas on lane 4. checksum for lane 4 . 0x0 r 0x42e compsum4_reg [7:0] ll_fcmp4 compu ted checksum on lane 4. computed checksum for lane 4 (see description for register 0x40e). 0x0 r 0x432 lid5_reg [7:5] reserved reserved. 0x0 r [4:0] ll_lid5 received ilas lid configuration on lane 5. lane identification for lane 5. 0x0 r 0x435 check sum5_reg [7:0] ll_fchk5 received checksum during ilas on lane 5. checksum for lane 5 . 0x0 r 0x436 compsum5_reg [7:0] ll_fcmp5 computed checksum on lane 5. computed checksum for lane 5 (see description for register 0x40e). 0x0 r
AD9164 data sheet rev. a | page 108 of 136 hex . addr . name bits bit name settings description reset access 0x43a lid6_reg [7:5] res erved reserved. 0x0 r [4:0] ll_lid6 received ilas lid configuration on lane 6. lane identification for lane 6. 0x0 r 0x43d checksum6_reg [7:0] ll_fchk6 received checksum during ilas on lane 6. checksum for lane 6 . 0x0 r 0x43e compsum6_reg [7:0] ll_ fcmp6 computed checksum on lane 6. computed checksum for lane 6 (see description for register 0x40e). 0x0 r 0x442 lid7_reg [7:5] reserved reserved. 0x0 r [4:0] ll_lid7 received ilas lid configuration on lane 7. lane identification for lane 7. 0x0 r 0x445 checksum7_reg [7:0] ll_fchk7 received checksum during ilas on lane 7. checksum for lane 7 . 0x0 r 0x446 compsum7_reg [7:0] ll_fcmp7 computed checksum on lane 5. computed checksum for lane 7 (see description for register 0x40e). 0x0 r 0x450 ils_di d [7:0] did d evice ( li nk) identification numbe r. did is the device id number . link information received on lane 0 as specified in section 8.3 of jesd204b. must be set to the value read in register 0x400 . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0x451 ils_bid [7:0] bid bank id, e xtension to did. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), an d must not be changed during normal operation. 0x0 r/w 0x452 ils_lid0 7 reserved reserved. 0x0 r 6 adjdir direction to adjust dac lmfc ( subclass 2 only). adjdir is the direction to adjust dac lmfc . link information received on lane 0 as specified in section 8.3 of jesd204b. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 5 phadj phase a djustment to dac ( subclass 2 only). phadj is the phase adj ustment request to the dac . link information received on lane 0 as specified in section 8.3 of jesd204b. this signal must onl y be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r /w [4:0] lid0 lane i dentification number (within link) . lid0 is the l ane identification for lane 0 . link information received on lane 0 as specified in section 8.3 of jesd204b. this signal must only be programmed while the qbd is held in soft reset (re gister 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w
data sheet AD9164 rev. a | page 109 of 136 hex . addr . name bits bit name settings description reset access 0x453 ils_scr_l 7 scr scramble enable. scr is the rx d e scrambling e nable . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1 r/w 0 descrambling is disabled. 1 descrambling is enabled. [6:5] reserved reserved. 0x0 r [4:0] l number of l anes per converter (minus 1) . l is the n umber of lanes per converter device . settings of 1, 2, 3, 4, 6 , and 8 are valid . refer to table 15 and table 16 . 0x7 r 0x454 ils_f [7:0] f number of octets per frame (minus 1) . this value of f is not used to soft configure the qbd. register ctrlreg1 is used to soft c onfigure the qbd. 0x0 r 0x455 ils_k [7:5] reserved reserved. 0x0 r [4:0] k number of frames per multiframe (minus 1) . k is the number of frames per multiframe . on this device, all modes us e k 32 (value in register is k 1). this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1f r/w 01111 16 frames per multiframe. 11111 32 frames pe r multiframe. 0x456 ils_m [7:0] m number of con verters per device (minus 1). m is the number of converters/device . settings of 1 and 2 are valid. refer to table 15 and t able 16 . 0x1 r 0x457 ils_cs_n [7:6] cs number of control bits per sample. cs is the n umber of control bits per sample . must be set to 0. control bits are not supported. 0x0 r 5 reserved reserved. 0x0 r [4:0] n converter r esolution (minus 1) . n i s the converter resolution . must be set to 16 (0x0f) . 0xf r 0x458 ils_np [7:5] subclassv device subclass version. subclas sv is the device s ubclass version . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), a nd must not be changed during normal operation. 0x0 r/w 000 subclass 0. 001 subclass 1. 010 subclass 2 ( n ot supported) . [4:0] np total number of bits per sample (minus 1) np is the total n umber of bits per sample . must be set to 16 (0x0f). re fer to table 15 and table 16 . 0xf r
AD9164 data sheet rev. a | page 110 of 136 hex . addr . name bits bit name settings description reset access 0x459 ils_s [7:5] jesdv jesd204 x version. jesdv is the jesd204 x version . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 000 jesd204a. 001 jesd204b. [4:0] s number of samples per converter per frame cycle (minus 1) . s is the number of samples per converte r per frame c ycle . settings of 1 and 2 are valid. refer to table 15 and table 16 . 0x1 r 0x45a ils_hd_cf 7 hd high density format. hd is the high density mode . refer to se ction 5.1.3 of jesd204b standard . 0x1 r 0 low density mode. 1 high density mode. [6:5] reserved reserved. 0x0 r [4:0] cf number of control bits per sample. cf is the number of control words per frame clock period per link . must be set to 0. control bits are not supported. 0x0 r 0x45b ils_res1 [7:0] res1 reserved. reserved field 1 . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0x45c ils_res2 [7:0] res2 reserved. reserved field 2 . this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0x45d ils_checksum [7:0] fchk0 link configura tion checksum. checksum for lane 0. the check - sum for the values programmed into register 0x450 to register 0x45c must be calculate d according to section 8.3 of the jesd204b spec ification and written to this register (sum(register 0x450 t o register 0x45c) 256). this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0x46c lane_deskew 7 ild7 inter l ane de skew status for lane 7 ( ignore t his output when no_ilas 1) . 0x0 r 0 de skew failed. 1 deskew achieved. 6 ils6 initial l ane s ynchronization status for lane 6 ( ignore t his output when no_ilas 1) . 0x0 r 0 synchronization lost. 1 synchronization achieved.
data sheet AD9164 rev. a | page 111 of 136 hex . addr . name bits bit name settings description reset access 5 ild5 interlane des kew status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 4 ild4 interlane deskew status for lane 4 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ild3 interlane deskew status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 2 ild2 interlane deskew status for lane 2 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 1 ild1 interlane deskew status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 0 ild0 interlane deskew status for lane 0 (ignore this output when no_ilas 1). 0x 0 r 0 deskew failed. 1 deskew achieved. 0x46d bad_disparity 7 bde7 bad d isparity error status for lane 7 . 0x0 r 0 error count eth [7:0] value. 1 error count eth [7:0] value. 6 bde6 bad d isparity error status for lane 6 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 bde5 bad d isparity errors status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 bde4 bad d isparity error status for lane 4 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 3 bde3 bad d isparity error status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 2 bde2 bad d isparity error status for lane 2 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 1 bde1 bad d isparity error status for lane 1 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 0 bde0 ba d d isparity error status for lane 0 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value.
AD9164 data sheet rev. a | page 112 of 136 hex . addr . name bits bit name settings description reset access 0x46e not_in_table 7 nit7 not i n t able error status for lane 7 . 0x0 r 0 error count eth[7:0] value. 1 error count eth [7:0] value. 6 nit6 not in table error status for lane 6 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 nit5 not in table errors status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 nit4 not in table error status for lane 4 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 3 nit3 not in table error status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 2 nit2 not in table error status for lane 2 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 1 nit1 not in table error status for lane 1 . 0x0 r 0 error count eth[7:0] va lue. 1 error count eth[7:0] value. 0 nit0 not in t able error status for lane 0 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 0x46f unexpected_kchar 7 uek7 unexpected k character error status for lane 7 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 uek6 unexpected k character error status for lane 6 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek5 unexpected k ch aracter error status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 uek4 unexpected k character error status for lane 4 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value . 3 uek3 unexpected k character error status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 2 uek2 unexpected k character error status for lane 2 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 1 uek1 unexpected k character error status for lane 1 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value.
data sheet AD9164 rev. a | page 113 of 136 hex . addr . name bits bit name settings description reset access 0 uek0 unexpected k character error status for lane 0 . 0x0 r 0 error c ount eth[7:0] value. 1 error count eth[7:0] value. 0x470 code_grp_sync 7 cgs7 code group sync status for lane 7 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 6 cgs6 code group sync status for lane 6 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 5 cgs5 code group sync status for lane 5 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 4 cgs4 code group sync status for lane 4 . 0x0 r 0 synchronization l ost. 1 synchronization achieved. 3 cgs3 code group sync status for lane 3 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cgs2 code group sync status for lane 2 . 0x0 r 0 synchronization lost. 1 synchr onization achieved. 1 cgs1 code group sync status for lane 1 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs0 code group sync status for lane 0 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x471 frame_sync 7 fs7 frame s ync status for lane 7 ( ignore this output when no_ilas 1) . 0x0 r 0 synchronization lost. 1 synchronization achieved. 6 fs6 frame sync status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 5 fs5 frame sync status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 4 fs4 frame sync status for lane 4 (ignor e this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved.
AD9164 data sheet rev. a | page 114 of 136 hex . addr . name bits bit name settings description reset access 3 fs3 frame sync status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 fs2 frame sync status for lane 2 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 1 fs1 frame sync status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 fs0 frame sync status for lane 0 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x472 good_checksum 7 cks7 computed c heck s um status for lane 7 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 6 cks6 computed checksum status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is corr ect. 5 cks5 computed checksum status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 4 cks4 computed checksum status for lane 4 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 3 cks3 computed checksum status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 2 cks2 computed checksum status for lan e 2 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 cks1 computed checksum status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is co rrect.
data sheet AD9164 rev. a | page 115 of 136 hex . addr . name bits bit name settings description reset access 0 cks0 computed checksum status for lane 0 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 0x473 init_lane_sync 7 ils7 initial lane s ynchronization status for lane 7 (ignore this out put when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 6 ils6 initial lane synchronization status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achi eved. 5 ils5 initial lane synchronization status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 4 ils4 initial lane synchronization status for lane 4 (ignore this output w hen no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 3 ils3 initial lane synchronization status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 ils2 initial lane synchronization status for lane 2 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 1 ils1 initial lane synchronization status for lane 1 (ignore this output when n o_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 ils0 initial lane synchronization status for lane 0 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 x475 ctrlreg0 7 rx_dis level input: disable deframer receiver when this input 1. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 1 disable cha racter replacement of /a/ and /f/ control characters at the end of received frames and multiframes. 0 enables the substitution.
AD9164 data sheet rev. a | page 116 of 136 hex . addr . name bits bit name settings description reset access 6 char_repl_dis when this input 1, character replacement at the end of frame/ m ulti f rame is disabled. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w [5:4] reserved reserved. 0x0 r 3 softrst soft reset. active high synchronous reset. resets all hardware to power - on state . 0x0 r/w 1 disables the deframer reception. 0 enable deframer logic. 2 forcesyncreq command from application to assert a s ync r equest ( syncout ). active high . 0x0 r/w 1 reserved reserved. 0x0 r 0 re pl_frm_ena when this l evel input is set, it enables replacement of frames received in error. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1 r/w 0x476 c trlreg1 [7:5] reserved reserved. 0x0 r 4 qual_rderr error reporting behavior for concurrent nit and rd errors. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal opera tion. 0x1 r/w 0 nit has no effect on rd error. 1 nit error masks concurrent rd error. 3 del_scr alternative descrambler enable. (see jesd204b section 5.2.4) this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3 ), and must not be changed during normal operation. 0x0 r/w 1 descrambling begins at octet 2 of user data. 0 descrambling begins at octet 0 of user data. this is the common usage. 2 cgs_sel determines the qbd behavior after c ode group sync has been achieved. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1 r/w 0 after code group sync is achieved, the qbd assert s syncout only if there are sufficient disparity errors as per the jesd 204b standard. 1 after code group sync is achieved, if a /k/ is followed by any character other than an /r/ or another /k/, qbd assert s syncout .
data sheet AD9164 rev. a | page 117 of 136 hex . addr . name bits bit name settings description reset access 1 no _ilas this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 1 for single - lane operation, ilas is omitted. code group sync is followed by user data. 0 code g roup s ync is followed by ilas. for multilane operation, no_ilas must always be set to 0. 0 fchk_n checksum calculation method. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , register 3), and must not be changed during normal operation. 0x0 r/w 0 calculate checksum by summing individual fields (this more closely matches the definition of the checksum field in the jesd204b standard . 1 calculate checksum by summing the registers containi ng the packed fields (this setting is provided in case the framer of another vendor performs the calculation with this method) . 0x477 ctrlreg2 7 ils_mode data l ink layer test mode. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0 normal mode. 1 code g roup sync pattern is followed by a perpetual ilas sequence. 6 reserved reserved. 0x0 r 5 repdatatest repetitive data test enable , using jtspat pattern. to enable the test, ils_ mode must 0. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 4 quetesterr queue t est e rror mode. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w 0 simultaneous errors on multiple lanes are reported as one error. 1 detected errors from all lanes are trapped in a counter and sequentially signaled on syncout .
AD9164 data sheet rev. a | page 118 of 136 hex . addr . name bits bit name settings description reset access 3 ar_ecntr automatic reset of error counter. the error counter that causes a ssertion of syncout is automati - cally reset to 0 when ar_ecntr 1. all other counters are unaffected. this signal must only be programmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x0 r/w [2:0] reserved reserved. 0x0 r 0x478 kval [7:0] ksync num ber of 4 k multiframes during ils. f is the number of octets per frame . settings of 1, 2, and 4 are valid. refer to table 15 and table 16 . this signal must only be progra mmed while the qbd is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0x1 r/w 0x47c errorthres [7:0] eth error t hreshold v alue. bad disparity, nit d isparity , and u nexpected k character errors are counted and c ompared to the e rror t hreshold value. when the count is equal, either an irq is generated or syncout is asserted per the mask register settings or both. function is performed in all lanes. this signal must only be programmed while the qb d is held in soft reset (register 0x475 , bit 3), and must not be changed during normal operation. 0xff r/w 0x47d sync_assert_mask [7:3] reserved reserved. 0x0 r [2:0] sync_assert_mask syncout assertion enable mask for bd, nit , and u ek error conditions. active high, syncout assertion enable mask for bd, nit , and uek error conditions, respectively. when an error counter, in any lane, has reached the error threshold count , eth[7:0], and the corresponding sync_assert_ m ask bit is set, syncout is asserted. the mask bits are as follows. note that the bit sequence is reversed with respect to the other error count controls and the error counters. 0x7 r/w bit 2 bad disparity error (bde) . bit 1 not i n table error (nit) . bit 0 unexpected k (uek) character error . 0x480 ecnt_ctrl0 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena0 error counter enable for lane 0. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not i n table error (nit) . bit 0 bad disparity error (bde) .
data sheet AD9164 rev. a | page 119 of 136 hex . addr . name bits bit name settings description reset access [2:0] ecnt_rst0 error counters enable for lane 0, active high. counters of each lane are addressed as follows: 0x7 r/w b it 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x481 ecnt_ctrl1 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena1 error counters enable for lane 1, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_rst1 error counters enable for lane 1, active high. count ers of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x482 ecnt_ctrl2 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena2 error counters enable for lane 2, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_ rst2 error counters enable for lane 2, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x483 ecn t_ctrl3 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena3 error counters enable for lane 3, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_rst3 error counters enable for lane 3, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit ) . bit 0 bad disparity error (bde) .
AD9164 data sheet rev. a | page 120 of 136 hex . addr . name bits bit name settings description reset access 0x484 ecnt_ctrl4 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena4 error counters enable for lane 4, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) ch aracter error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_rst4 error counters enable for lane 4, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek ) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x485 ecnt_ctrl5 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena5 error counters enable for lane 5, active high. counters of each lane are address ed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_rst5 error counters enable for lane 5, active high. counters of each lane are add ressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x486 ecnt_ctrl6 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena6 error counters enable for lane 6, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . [2:0] ecnt_rst6 error counters ena ble for lane 6, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x487 ecnt_ctrl7 [7:6] reserved reserved. 0x0 r [5:3] ecnt_ena7 error counters enable for lane 7, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad dispa rity error (bde) .
data sheet AD9164 rev. a | page 121 of 136 hex . addr . name bits bit name settings description reset access [2:0] ecnt_rst7 reset error counters for lane 7, active high. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad di sparity error (bde) . 0x488 ecnt_tch0 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch0 terminal c ount hold enable of error counters for lane 0. when set, the designated counter is to hold the t erminal c ount value of 0xff when it is reached until the c ounter is reset by the user. oth - erwis e , the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity e rror (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x489 ecnt_tch1 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch1 terminal count hold enable of error counters for lane 1. when set, the designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset by the user. otherwise, the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x48a ecnt_tch2 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch2 terminal count hold enable of error counters for lane 2. when set, the designated counter is to hold the terminal count value of 0xf f when it is reached until the counter is reset by the user. otherwise, the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) .
AD9164 data sheet rev. a | page 122 of 136 hex . addr . name bits bit name settings description reset access this signal must only be pro - grammed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x48b ecnt_tch3 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch3 terminal count hold enable of error counters for lane 3. when set, the designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset by the user. otherwise, the designated counter rolls over. count ers of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x48c ecnt_tch4 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch4 terminal count hold enable of error counters for lane 4. when set, the designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset by the user. otherwise, the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bi t 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x48d ecnt_tch5 [7:3] re served reserved. 0x0 r [2:0] ecnt_tch5 terminal count hold enable of error counters for lane 5. when set, the designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset by the user. otherwise, the desi gnated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be prog rammed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation.
data sheet AD9164 rev. a | page 123 of 136 hex . addr . name bits bit name settings description reset access 0x48e ecnt_tch6 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch6 terminal count hold enable of error counters for lane 6. when set, t he designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset by the user. otherwise, the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (u ek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operati on. 0x48f ecnt_tch7 [7:3] reserved reserved. 0x0 r [2:0] ecnt_tch7 terminal count hold enable of error counters for lane 7. when set, the designated counter is to hold the terminal count value of 0xff when it is reached until the counter is reset b y the user. otherwise, the designated counter rolls over. counters of each lane are addressed as follows: 0x7 r/w bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . this signal must only be programmed while the qbd is held in soft reset (register 0x475, bit 3), and must not be changed during normal operation. 0x490 ecnt_stat0 [7:4] reserved reserved. 0x0 r 3 lane_ena0 this output indicates if l ane 0 is enable d. 0x0 r 0 lane 0 is held in soft reset. 1 lane 0 is enabled. [2:0] ecnt_tcr0 terminal c ount r eached indicator of error counters for lane 0. set to 1 when the corresponding counter t erminal c ount val u e of 0 xff has been reached. counters o f each lane are addressed as follows. 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x491 ecnt_stat1 [7:4] reserved reserved. 0x0 r 3 lane_ena1 this outp ut indicates if lane 1 is enabled. 0x0 r 0 lane 1 is held in soft reset. 1 lane 1 is enabled.
AD9164 data sheet rev. a | page 124 of 136 hex . addr . name bits bit name settings description reset access [2:0] ecnt_tcr1 terminal count reached indicator of error counters for lane 1. set to 1 when the corresponding counter terminal count value of 0 xff has been reached. counters of each lane are addressed as follows. 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x492 ecnt_stat2 [7:4] reserved reserved. 0x0 r 3 lane_ena2 this output indicates if lane 2 is enabled. 0x0 r 0 lane 2 is held in soft reset. 1 lane 2 is enabled. [2:0] ecnt_tcr2 terminal count reached indicator of error counters for lane 2. set to 1 when the corresponding c ounter terminal count value of 0xff has been reached. counters of each lane are addressed as follows. 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x493 ecnt _stat3 [7:4] reserved reserved. 0x0 r 3 lane_ena3 this output indicates if lane 3 is enabled. 0x0 r 0 lane 3 is held in soft reset. 1 lane 3 is enabled. [2:0] ecnt_tcr3 terminal count reached indicator of error counters for lane 3. s et to 1 when the corresponding counter terminal count value of 0xff has been reached. counters of each lane are addressed as follows: 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disp arity error (bde) . 0x494 ecnt_stat4 [7:4] reserved reserved. 0x0 r 3 lane_ena4 this output indicates if lane 4 is enabled. 0x0 r 0 lane 4 is held in soft reset. 1 lane 4 is enabled. [2:0] ecnt_tcr4 terminal count reached indicator of error counters for lane 4. set to 1 when the corresponding counter terminal count value of 0xff has been reached. counters of each lane are addressed as follows : 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) .
data sheet AD9164 rev. a | page 125 of 136 hex . addr . name bits bit name settings description reset access 0x495 ecnt_stat5 [7:4] reserved reserved. 0x0 r 3 lane_ena5 this output indicates if lane 5 is enabled. 0x0 r 0 lane 5 is held in soft reset. 1 lane 5 is enabled. [2:0] ecnt_tcr5 terminal count reached indicator of error counters for lane 5. set to 1 when the corresponding counter terminal count value of 0xff has been reached. counters of each lane are addressed as follows : 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x496 ecnt_stat6 [7:4] reserved reserved. 0x0 r 3 lane_ena6 this output indicates if lane 6 is enabled. 0x0 r 0 lane 6 is held in soft reset. 1 lane 6 is enabled. [2:0] ecnt_tcr6 terminal count reached indicator of error counters for lane 6. set to 1 when the corresponding counter terminal count value of 0xff has been reached. counters of each lane are addressed as follows : 0x0 r bit 2 unexpe cted k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x497 ecnt_stat7 [7:4] reserved reserved. 0x0 r 3 lane_ena7 this output indicates if lane 7 is enabled. 0x0 r 0 lane 7 is held i n soft reset. 1 lane 7 is enabled. [2:0] ecnt_tcr7 terminal count reached indicator of error counters for lane 7. set to 1 when the corresponding counter terminal count value of 0xff has been reached. counters of each lane are addressed as fol lows : 0x0 r bit 2 unexpected k (uek) character error . bit 1 not in table error (nit) . bit 0 bad disparity error (bde) . 0x4b0 link_status0 7 bde0 bad d isparity errors status for lane 0 . 0x0 r 0 error count eth [7:0] val ue. 1 error count eth [7:0] value. 6 nit0 no t in t able errors status for lane 0 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek0 unexpected k character errors status for lane 0 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value.
AD9164 data sheet rev. a | page 126 of 136 hex . addr . name bits bit name settings description reset access 4 ild0 interlane deskew status for lane 0 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils0 initial l ane s ynchronization status for lane 0 ( ignore t his ou tput when no_ilas 1) . 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks0 computed checksum status for lane 0 ( ignore t his output when no_ilas 1) . 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 f s0 frame sync status for lane 0 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs0 code g roup s ync status for lane 0 . 0x0 r 0 synchronization lost. 1 synchronization achiev ed. 0x4b1 link_status1 7 bde1 bad disparity errors status for lane 1 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 nit1 not in table errors status for lane 1 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek1 unexpected k character errors status for lane 1 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 ild1 interlane deskew status for lane 1 (ignore this output when no_il as 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils1 initial lane synchronization status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks1 computed ch ecksum status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 fs1 frame sync status for lane 1 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 sy nchronization achieved.
data sheet AD9164 rev. a | page 127 of 136 hex . addr . name bits bit name settings description reset access 0 cgs1 code group sync status for lane 1 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x4b2 link_status2 7 bde2 bad disparity errors status for lane 2 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 nit2 not in table errors status for lane 2 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek2 unexpected k character errors status for lane 2 . 0x0 r 0 error count eth [7:0] value. 1 error count eth[7:0] value. 4 ild2 inter l ane d eskew status for lane 2 ( ignore t his output when no_ilas 1) . 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils2 initial lane synchronization status for lane 2 (ig nore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks2 computed checksum status for lane 2 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is corre ct. 1 fs2 frame sync status for lane 2 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs2 code group sync status for lane 2 . 0x0 r 0 synchronization lost. 1 synchroniz ation achieved. 0x4b3 link_status3 7 bde3 bad disparity errors status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 nit3 not in table errors status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek3 unexpected k character errors status for lane 3 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 ild3 interlane deskew status for lane 3 (ignore this outpu t when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved.
AD9164 data sheet rev. a | page 128 of 136 hex . addr . name bits bit name settings description reset access 3 ils3 initial lane synchronization status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks3 computed checksum status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 fs3 frame sync status for lane 3 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs3 code group sync status for lane 3 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x4b4 link_status4 7 bde4 bad disparity errors status for lane 4 . 0x0 r 0 error count eth[7 :0] value. 1 error count eth[7:0] value. 6 nit4 not in table errors status for lane 4 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek4 unexpected k character errors status for lane 4 . 0x0 r 0 error count eth [7:0] value. 1 error count eth[7:0] value. 4 ild4 interlane deskew status for lane 4 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils4 initial lane synchronization status for lane 4 (ig nore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks4 computed checksum status for lane 4 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is corre ct. 1 fs4 frame sync status for lane 4 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs4 code group sync status for lane 4 . 0x0 r 0 synchronization lost. 1 synchroniz ation achieved.
data sheet AD9164 rev. a | page 129 of 136 hex . addr . name bits bit name settings description reset access 0x4b5 link_status5 7 bde5 bad d isparity errors status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 nit5 not in table errors status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek5 unexpected k character errors status for lane 5 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 ild5 interlane deskew status for lane 5 (ignore this outpu t when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils5 initial lane synchronization status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks5 computed checksum status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 fs5 frame sync status for lane 5 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs5 code group sync status for lane 5 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x4b6 link_status6 7 bde6 bad disparity errors status for lane 6 . 0x0 r 0 error count eth[7 :0] value. 1 error count eth[7:0] value. 6 nit6 not in table errors status for lane 6 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek6 unexpected k character errors status for lane 6 . 0x0 r 0 error count eth [7:0] value. 1 error count eth[7:0] value. 4 ild6 interlane deskew status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils6 initial lane synchronization status for lane 6 (ig nore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved.
AD9164 data sheet rev. a | page 130 of 136 hex . addr . name bits bit name settings description reset access 2 cks6 computed checksum status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is corre ct. 1 fs6 frame sync status for lane 6 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs6 code group sync status for lane 6 . 0x0 r 0 synchronization lost. 1 synchroniz ation achieved. 0x4b7 link_status7 7 bde7 bad disparity errors status for lane 7 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 6 nit7 not in table errors status for lane 7 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 5 uek7 unexpected k character errors status for lane 7 . 0x0 r 0 error count eth[7:0] value. 1 error count eth[7:0] value. 4 ild7 interlane deskew status for lane 7 (ignore this outpu t when no_ilas 1). 0x0 r 0 deskew failed. 1 deskew achieved. 3 ils7 initial lane synchronization status for lane 7 (ignore this output when no_ilas 1). 0x0 r 0 synchronization lost. 1 synchronization achieved. 2 cks7 computed checksum status for lane 7 (ignore this output when no_ilas 1). 0x0 r 0 checksum is incorrect. 1 checksum is correct. 1 fs7 frame s ync status for lane 7 ( ignore t his output when no_ilas 1) . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0 cgs7 code group sync status for lane 7 . 0x0 r 0 synchronization lost. 1 synchronization achieved. 0x4b8 jesd_irq_enablea 7 en_bde bad d isparity error counter . 0x0 r/w 6 en_nit not in t able err or counter . 0x0 r/w 5 en_uek unexpected k error counter . 0x0 r/w 4 en_ild inter lane d eskew . 0x0 r/w 3 en_ils initial l ane s ync . 0x0 r/w
data sheet AD9164 rev. a | page 131 of 136 hex . addr . name bits bit name settings description reset access 2 en_cks good checks um. this is an interrupt that compares two checksums: t he checksum that the transmit ter sen t over the link during the ilas , and t he checksum that the receiver calculated from the ilas data that the transmitter sent over the link. note that the checksum irq never at any time looks at the checksum that is programmed over the spi into regist er 0x45 d . the checksum irq only looks at the data sent by the transmitter, and never looks at any data programmed via the spi. 0x0 r/w 1 en_fs frame s ync . 0x0 r/w 0 en_cgs code g roup s ync . 0x0 r/w 0x4b9 jesd_irq_enableb [7:1] reserved reserved. 0 x0 r 0 en_ilas configuration m is m atch (checked for lane 0 only) . the ilas irq compares the two sets of ilas data that the receiver has : t he ilas data sent over the jesd 204b link by the transmitter , and t he ilas data programmed into the receiver via the spi (r egister 0x450 to register 0x45d) . if the data differ s , the irq is triggered. note that all of the ilas data (including the checksum) is compared. 0x0 r/w 0x4ba jesd_irq_statusa 7 irq_bde bad d isparity error counter . 0x0 r/w 6 irq_nit not in ta ble error counter . 0x0 r/w 5 irq_uek unexpected k error counter . 0x0 r/w 4 irq_ild interlane deskew. 0x0 r/w 3 irq_ils initial lane sync. 0x0 r/w 2 irq_cks good c heck s um . 0x0 r/w 1 irq_fs frame s ync . 0x0 r/w 0 irq_cgs code g roup s yn c . 0x0 r/w 0x4bb jesd_irq_statusb [7:1] reserved reserved. 0x0 r 0 irq_ilas configuration m is m atch (checked for lane 0 only) . 0x0 r/w 0x800 hopf_ctrl [7:6] hopf_mode frequency switch mode . 0x0 r/w 00 phase continuous switch. changes frequency tuning word , and the phase accumulator continues to accumulate to the new ftw. 01 phase dis continuous switch. changes the frequency tuning word and resets the phase accumulator. 10 reserved . 5 reserved reserved. 0x0 r [4:0] hopf_sel hopping frequency selection control. enter the number of the ftw to select the output of that nco. 0x0 r/w 0x806 hopf_ftw1_0 [7:0] hopf_ftw1[7:0] hopping frequency ftw1 . 0x0 r/w 0x807 hopf_ftw1_1 [7:0] hopf_ftw1[15:8] hopping frequency ftw1 . 0x0 r/w
AD9164 data sheet rev. a | page 132 of 136 hex . addr . name bits bit name settings description reset access 0x808 hopf_ftw1_2 [7:0] hopf_ftw1[23:16] hopping frequency ftw1 0x0 r/w 0x809 hopf_ftw1_3 [7:0] hopf_ftw1[31:24] hopping frequency ftw1 0x0 r/w 0x80a hopf_ftw2_0 [7:0] hopf_ftw2[7:0] hopping frequency ftw2 0x0 r/w 0x80b hopf_ftw2_1 [7:0] hopf_ftw2[1 5:8] hopping frequency ftw2 0x0 r/w 0x80c hopf_ftw2_2 [7:0] hopf_ftw2[23:16] hopping frequency ftw2 0x0 r/w 0x80d hopf_ftw2_3 [7:0] hopf_ftw2[31:24] hopping frequency ftw2 0x0 r/w 0x80e hopf_ftw3_0 [7:0] hopf_ftw3[7:0] hopping frequency ftw3 0x0 r/w 0x80f hopf_ftw3_1 [7:0] hopf_ftw3[15:8] hopping frequency ftw3 0x0 r/w 0x810 hopf_ftw3_2 [7:0] hopf_ftw3[23:16] hopping frequency ftw3 0x0 r/w 0x811 hopf_ftw3_3 [7:0] hopf_ftw3[31:24] hopping frequency ftw3 0x0 r/w 0x812 hopf_ftw4_0 [7:0] hopf_ftw4 [7:0] hopping frequency ftw4 0x0 r/w 0x813 hopf_ftw4_1 [7:0] hopf_ftw4[15:8] hopping frequency ftw4 0x0 r/w 0x814 hopf_ftw4_2 [7:0] hopf_ftw4[23:16] hopping frequency ftw4 0x0 r/w 0x815 hopf_ftw4_3 [7:0] hopf_ftw4[31:24] hopping frequency ftw4 0x0 r /w 0x816 hopf_ftw5_0 [7:0] hopf_ftw5[7:0] hopping frequency ftw5 0x0 r/w 0x817 hopf_ftw5_1 [7:0] hopf_ftw5[15:8] hopping frequency ftw5 0x0 r/w 0x818 hopf_ftw5_2 [7:0] hopf_ftw5[23:16] hopping frequency ftw5 0x0 r/w 0x819 hopf_ftw5_3 [7:0] hopf_ftw5 [31:24] hopping frequency ftw5 0x0 r/w 0x81a hopf_ftw6_0 [7:0] hopf_ftw6[7:0] hopping frequency ftw6 0x0 r/w 0x81b hopf_ftw6_1 [7:0] hopf_ftw6[15:8] hopping frequency ftw6 0x0 r/w 0x81c hopf_ftw6_2 [7:0] hopf_ftw6[23:16] hopping frequency ftw6 0x0 r /w 0x81d hopf_ftw6_3 [7:0] hopf_ftw6[31:24] hopping frequency ftw6 0x0 r/w 0x81e hopf_ftw7_0 [7:0] hopf_ftw7[7:0] hopping frequency ftw7 0x0 r/w 0x81f hopf_ftw7_1 [7:0] hopf_ftw7[15:8] hopping frequency ftw7 0x0 r/w 0x820 hopf_ftw7_2 [7:0] hopf_ftw7 [23:16] hopping frequency ftw7 0x0 r/w 0x821 hopf_ftw7_3 [7:0] hopf_ftw7[31:24] hopping frequency ftw7 0x0 r/w 0x822 hopf_ftw8_0 [7:0] hopf_ftw8[7:0] hopping frequency ftw8 0x0 r/w 0x823 hopf_ftw8_1 [7:0] hopf_ftw8[15:8] hopping frequency ftw8 0x0 r /w 0x824 hopf_ftw8_2 [7:0] hopf_ftw8[23:16] hopping frequency ftw8 0x0 r/w 0x825 hopf_ftw8_3 [7:0] hopf_ftw8[31:24] hopping frequency ftw8 0x0 r/w 0x826 hopf_ftw9_0 [7:0] hopf_ftw9[7:0] hopping frequency ftw9 0x0 r/w 0x827 hopf_ftw9_1 [7:0] hopf_ftw 9[15:8] hopping frequency ftw9 0x0 r/w 0x828 hopf_ftw9_2 [7:0] hopf_ftw9[23:16] hopping frequency ftw9 0x0 r/w 0x829 hopf_ftw9_3 [7:0] hopf_ftw9[31:24] hopping frequency ftw9 0x0 r/w 0x82a hopf_ftw10_0 [7:0] hopf_ftw10[7:0] hopping frequency ftw10 0 x0 r/w 0x82b hopf_ftw10_1 [7:0] hopf_ftw10[15:8] hopping frequency ftw10 0x0 r/w 0x82c hopf_ftw10_2 [7:0] hopf_ftw10[23:16] hopping frequency ftw10 0x0 r/w 0x82d hopf_ftw10_3 [7:0] hopf_ftw10[31:24] hopping frequency ftw10 0x0 r/w 0x82e hopf_ftw11_0 [7:0] hopf_ftw11[7:0] hopping frequency ftw11 0x0 r/w 0x82f hopf_ftw11_1 [7:0] hopf_ftw11[15:8] hopping frequency ftw11 0x0 r/w 0x830 hopf_ftw11_2 [7:0] hopf_ftw11[23:16] hopping frequency ftw11 0x0 r/w 0x831 hopf_ftw11_3 [7:0] hopf_ftw11[31:24] ho pping frequency ftw11 0x0 r/w 0x832 hopf_ftw12_0 [7:0] hopf_ftw12[7:0] hopping frequency ftw12 0x0 r/w 0x833 hopf_ftw12_1 [7:0] hopf_ftw12[15:8] hopping frequency ftw12 0x0 r/w
data sheet AD9164 rev. a | page 133 of 136 hex . addr . name bits bit name settings description reset access 0x834 hopf_ftw12_2 [7:0] hopf_ftw12[23:16] hopping frequency ftw12 0x0 r/ w 0x835 hopf_ftw12_3 [7:0] hopf_ftw12[31:24] hopping frequency ftw12 0x0 r/w 0x836 hopf_ftw13_0 [7:0] hopf_ftw13[7:0] hopping frequency ftw13 0x0 r/w 0x837 hopf_ftw13_1 [7:0] hopf_ftw13[15:8] hopping frequency ftw13 0x0 r/w 0x838 hopf_ftw13_2 [7:0] hopf_ftw13[23:16] hopping frequency ftw13 0x0 r/w 0x839 hopf_ftw13_3 [7:0] hopf_ftw13[31:24] hopping frequency ftw13 0x0 r/w 0x83a hopf_ftw14_0 [7:0] hopf_ftw14[7:0] hopping frequency ftw14 0x0 r/w 0x83b hopf_ftw14_1 [7:0] hopf_ftw14[15:8] hopping f requency ftw14 0x0 r/w 0x83c hopf_ftw14_2 [7:0] hopf_ftw14[23:16] hopping frequency ftw14 0x0 r/w 0x83d hopf_ftw14_3 [7:0] hopf_ftw14[31:24] hopping frequency ftw14 0x0 r/w 0x83e hopf_ftw15_0 [7:0] hopf_ftw15[7:0] hopping frequency ftw15 0x0 r/w 0x8 3f hopf_ftw15_1 [7:0] hopf_ftw15[15:8] hopping frequency ftw15 0x0 r/w 0x840 hopf_ftw15_2 [7:0] hopf_ftw15[23:16] hopping frequency ftw15 0x0 r/w 0x841 hopf_ftw15_3 [7:0] hopf_ftw15[31:24] hopping frequency ftw15 0x0 r/w 0x842 hopf_ftw16_0 [7:0] hopf _ftw16[7:0] hopping frequency ftw16 0x0 r/w 0x843 hopf_ftw16_1 [7:0] hopf_ftw16[15:8] hopping frequency ftw16 0x0 r/w 0x844 hopf_ftw16_2 [7:0] hopf_ftw16[23:16] hopping frequency ftw16 0x0 r/w 0x845 hopf_ftw16_3 [7:0] hopf_ftw16[31:24] hopping frequ ency ftw16 0x0 r/w 0x846 hopf_ftw17_0 [7:0] hopf_ftw17[7:0] hopping frequency ftw17 0x0 r/w 0x847 hopf_ftw17_1 [7:0] hopf_ftw17[15:8] hopping frequency ftw17 0x0 r/w 0x848 hopf_ftw17_2 [7:0] hopf_ftw17[23:16] hopping frequency ftw17 0x0 r/w 0x849 ho pf_ftw17_3 [7:0] hopf_ftw17[31:24] hopping frequency ftw17 0x0 r/w 0x84a hopf_ftw18_0 [7:0] hopf_ftw18[7:0] hopping frequency ftw18 0x0 r/w 0x84b hopf_ftw18_1 [7:0] hopf_ftw18[15:8] hopping frequency ftw18 0x0 r/w 0x84c hopf_ftw18_2 [7:0] hopf_ftw18[ 23:16] hopping frequency ftw18 0x0 r/w 0x84d hopf_ftw18_3 [7:0] hopf_ftw18[31:24] hopping frequency ftw18 0x0 r/w 0x84e hopf_ftw19_0 [7:0] hopf_ftw19[7:0] hopping frequency ftw19 0x0 r/w 0x84f hopf_ftw19_1 [7:0] hopf_ftw19[15:8] hopping frequency ft w19 0x0 r/w 0x850 hopf_ftw19_2 [7:0] hopf_ftw19[23:16] hopping frequency ftw19 0x0 r/w 0x851 hopf_ftw19_3 [7:0] hopf_ftw19[31:24] hopping frequency ftw19 0x0 r/w 0x852 hopf_ftw20_0 [7:0] hopf_ftw20[7:0] hopping frequency ftw20 0x0 r/w 0x853 hopf_ftw 20_1 [7:0] hopf_ftw20[15:8] hopping frequency ftw20 0x0 r/w 0x854 hopf_ftw20_2 [7:0] hopf_ftw20[23:16] hopping frequency ftw20 0x0 r/w 0x855 hopf_ftw20_3 [7:0] hopf_ftw20[31:24] hopping frequency ftw20 0x0 r/w 0x856 hopf_ftw21_0 [7:0] hopf_ftw21[7:0] hopping frequency ftw21 0x0 r/w 0x857 hopf_ftw21_1 [7:0] hopf_ftw21[15:8] hopping frequency ftw21 0x0 r/w 0x858 hopf_ftw21_2 [7:0] hopf_ftw21[23:16] hopping frequency ftw21 0x0 r/w 0x859 hopf_ftw21_3 [7:0] hopf_ftw21[31:24] hopping frequency ftw21 0x0 r/w 0x85a hopf_ftw22_0 [7:0] hopf_ftw22[7:0] hopping frequency ftw22 0x0 r/w 0x85b hopf_ftw22_1 [7:0] hopf_ftw22[15:8] hopping frequency ftw22 0x0 r/w 0x85c hopf_ftw22_2 [7:0] hopf_ftw22[23:16] hopping frequency ftw22 0x0 r/w 0x85d hopf_ftw22_3 [7:0] hopf_ftw22[31:24] hopping frequency ftw22 0x0 r/w 0x85e hopf_ftw23_0 [7:0] hopf_ftw23[7:0] hopping frequency ftw23 0x0 r/w 0x85f hopf_ftw23_1 [7:0] hopf_ftw23[15:8] hopping frequency ftw23 0x0 r/w
AD9164 data sheet rev. a | page 134 of 136 hex . addr . name bits bit name settings description reset access 0x860 hopf_ftw23_2 [7:0] hopf_ftw23[23:16] hop ping frequency ftw23 0x0 r/w 0x861 hopf_ftw23_3 [7:0] hopf_ftw23[31:24] hopping frequency ftw23 0x0 r/w 0x862 hopf_ftw24_0 [7:0] hopf_ftw24[7:0] hopping frequency ftw24 0x0 r/w 0x863 hopf_ftw24_1 [7:0] hopf_ftw24[15:8] hopping frequency ftw24 0x0 r/w 0x864 hopf_ftw24_2 [7:0] hopf_ftw24[23:16] hopping frequency ftw24 0x0 r/w 0x865 hopf_ftw24_3 [7:0] hopf_ftw24[31:24] hopping frequency ftw24 0x0 r/w 0x866 hopf_ftw25_0 [7:0] hopf_ftw25[7:0] hopping frequency ftw25 0x0 r/w 0x867 hopf_ftw25_1 [7:0] hopf_ftw25[15:8] hopping frequency ftw25 0x0 r/w 0x868 hopf_ftw25_2 [7:0] hopf_ftw25[23:16] hopping frequency ftw25 0x0 r/w 0x869 hopf_ftw25_3 [7:0] hopf_ftw25[31:24] hopping frequency ftw25 0x0 r/w 0x86a hopf_ftw26_0 [7:0] hopf_ftw26[7:0] hopping f requency ftw26 0x0 r/w 0x86b hopf_ftw26_1 [7:0] hopf_ftw26[15:8] hopping frequency ftw26 0x0 r/w 0x86c hopf_ftw26_2 [7:0] hopf_ftw26[23:16] hopping frequency ftw26 0x0 r/w 0x86d hopf_ftw26_3 [7:0] hopf_ftw26[31:24] hopping frequency ftw26 0x0 r/w 0x 86e hopf_ftw27_0 [7:0] hopf_ftw27[7:0] hopping frequency ftw27 0x0 r/w 0x86f hopf_ftw27_1 [7:0] hopf_ftw27[15:8] hopping frequency ftw27 0x0 r/w 0x870 hopf_ftw27_2 [7:0] hopf_ftw27[23:16] hopping frequency ftw27 0x0 r/w 0x871 hopf_ftw27_3 [7:0] hopf_ ftw27[31:24] hopping frequency ftw27 0x0 r/w 0x872 hopf_ftw28_0 [7:0] hopf_ftw28[7:0] hopping frequency ftw28 0x0 r/w 0x873 hopf_ftw28_1 [7:0] hopf_ftw28[15:8] hopping frequency ftw28 0x0 r/w 0x874 hopf_ftw28_2 [7:0] hopf_ftw28[23:16] hopping freque ncy ftw28 0x0 r/w 0x875 hopf_ftw28_3 [7:0] hopf_ftw28[31:24] hopping frequency ftw28 0x0 r/w 0x876 hopf_ftw29_0 [7:0] hopf_ftw29[7:0] hopping frequency ftw29 0x0 r/w 0x877 hopf_ftw29_1 [7:0] hopf_ftw29[15:8] hopping frequency ftw29 0x0 r/w 0x878 hop f_ftw29_2 [7:0] hopf_ftw29[23:16] hopping frequency ftw29 0x0 r/w 0x879 hopf_ftw29_3 [7:0] hopf_ftw29[31:24] hopping frequency ftw29 0x0 r/w 0x87a hopf_ftw30_0 [7:0] hopf_ftw30[7:0] hopping frequency ftw30 0x0 r/w 0x87b hopf_ftw30_1 [7:0] hopf_ftw30[ 15:8] hopping frequency ftw30 0x0 r/w 0x87c hopf_ftw30_2 [7:0] hopf_ftw30[23:16] hopping frequency ftw30 0x0 r/w 0x87d hopf_ftw30_3 [7:0] hopf_ftw30[31:24] hopping frequency ftw30 0x0 r/w 0x87e hopf_ftw31_0 [7:0] hopf_ftw31[7:0] hopping frequency ft w31 0x0 r/w 0x87f hopf_ftw31_1 [7:0] hopf_ftw31[15:8] hopping frequency ftw31 0x0 r/w 0x880 hopf_ftw31_2 [7:0] hopf_ftw31[23:16] hopping frequency ftw31 0x0 r/w 0x881 hopf_ftw31_3 [7:0] hopf_ftw31[31:24] hopping frequency ftw31 0x0 r/w
data sheet AD9164 rev. a | page 135 of 136 outline di mensions 0.50 bsc 7.00 ref sq 5.895 bsc 5.85 bsc 8.05 8.00 sq 7.95 10-28-2014- a 0.50 ref 0.24 ref a b c d e f g 9 10 8 11 12 13 14 15 7 5 6 4 2 3 1 bottom view h j k l m n p r detail a top view coplanarity 0.08 0.35 0.30 0.25 ball diameter seating plane a1 ball corner a1 ball corner 0.35 0.30 0.25 0.22 nom 0.15 min 0.86 max 0.76 mom pkg-004576 detail a figure 143 . 165 - ball chip scale package ball grid array [csp_bga] (bc - 165 - 1) dimensions shown in millimeters 07-10-2015-a 0.31 nom 0.21 min a b c d e f g 1 3 2 4 6 5 7 8 9 10 11 12 13 bot t om view h j k l m n detail a t op view ball diameter a1 ball pad corner pkg-004675 a1 ball corner 1 1.05 1 1.00 sq 10.95 * 0.95 max detail a 5.935 bsc 1.285 bsc 5.890 bsc 2.405 bsc 0.35 0.30 0.25 seating plane 0.45 0.40 0.35 coplanarit y 0.12 9.60 ref sq 0.80 bsc 0.70 ref * compliant to jedec standards mo-275-ffac-1 with the exception of package height and thickness. figure 144 . 169 - ball chip scale package ball grid array [csp_bga] (bc - 169 - 2) dimens ions shown in millimeters
AD9164 data sheet rev. a | page 136 of 136 ordering guide model 1 te mperature range package description package option AD9164 b bc z ?40c to +85c 165- ball chip scale package ball grid array [csp_bga] bc -165-1 AD9164 bbczrl ?40c to +85c 165- ball chip scale package ball grid array [csp_bga] bc -165-1 AD9164 b bc a z ?40c to +85c 169- ball chip scale package ball grid array [ csp _ bga ] bc -1 69-2 AD9164 bbca zrl ?40c to +85c 169- ball chip scale package ball grid array (csp_bga) bc -169-2 ad916 4 bbca ?40c to +85c 169- ball chip scale package ball grid array [csp_bga] bc -169-2 AD9164 b bc a rl ?40c to +85c 169- ball chip scale package ball grid a rray [csp _ bga] bc -169-2 AD9164 - fmc - ebz evaluation board for 8 8 mm package with high accuracy balance balun AD9164 - fmcb - ebz evaluation board for 8 8 mm package with balun and match optimized for wider output bandwidth AD9164 - fmcc - ebz evaluatio n board 1 z = rohs compliant part. ? 2016 C 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14414 - 0 - 1/17(a)

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